Liquid crystal display device
AssigneeHitachi, Ltd.
InventorsMasuyuki Ohta, Masahiro Ishi, Kikuo Ono, Nobuyuki Suzuki
Life of this patent
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Abstract
An active matrix type liquid crystal display device includes first and second substrates with a liquid crystal layer therebetween, a plurality of drain lines and gate lines formed on the first substrate and crossing each other in a matrix form, a plurality of pixels formed by adjoining the drain lines and the gate lines, and at least a pixel electrode formed on the first substrate in each pixel, first reference line is arranged along one of the adjoining gate lines, a second reference line is arranged along another of the adjoining gate lines, and the pixel electrode crosses only one of the first reference line and the second reference line.
Claims21
An active matrix type liquid crystal display device comprising:
- a first and a second substrate with a liquid crystal layer therebetween;
- a plurality of drain lines and gate lines formed on the first substrate and crossing each other in a matrix form;
- a plurality of pixels formed by adjoining said drain lines and said gate lines;
- and
- at least one pixel electrode formed on the first substrate in each pixel;
- wherein a first reference line arranged along one of the adjoining gate lines, a second reference line is arranged along another of the adjoining gate lines, and the at least one pixel electrode crosses only one of the first reference line and the second reference line.
An active matrix liquid crystal display device comprising:
- first and second substrates with a liquid crystal layer therebetween;
- a plurality of drain lines and gate lines formed on the first substrate and crossing each other in a matrix form;
- a plurality of pixels formed by adjoining said drain lines and said gate lines;
- at least a pixel electrode formed on the first substrate in each pixel;
- a source electrode, a drain electrode, and a gate electrode forming a thin film transistor;
- wherein a first reference line enabling formation of a storage capacitance is arranged in each pixel and near one of the adjoining gate lines, a second reference line is arranged nearer to an other of the adjoining gate lines than the first reference line, and the storage capacitance is formed on the first reference line.
Dependencies are inferred from the claim text.