DRAM operating like SRAM
AssigneeFujitsu Limited
InventorsToshiya Miyo, Toshikazu Nakamura, Satoshi Eto, Ayako Sato, Masato Matsumiya
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.
Claims8
A semiconductor memory device, comprising:
- a first bit line connected to a memory cell via a transistor;
- a transfer gate;
- a second bit line connected to said first bit line via said transfer gate;
- a sense amplifier connected to said second bit line;
- a first precharge circuit for precharging said first bit line;
- a second precharge circuit for precharging said second bit line;
- a control circuit which precharges said first bit line by said first precharge circuit after closing said transfer gate, followed by subsequent precharging of said second bit line by said second precharge circuit.
A method of precharging a semiconductor memory device, comprising the steps of:
- decoupling bit lines of a memory cell portion from bit lines of a sense amplifier portion;
- precharging the bit lines of the memory cell portion while maintaining data of sense amplifiers;
- precharging the bit lines of the sense amplifier portion after precharging the bit lines of the memory cell portion;
- reading data from the sense amplifiers at different column addresses on an identical row address during a time period between the precharging of the bit lines of the memory cell portion and the precharging of the bit lines of the sense amplifier portion.
A semiconductor memory device, comprising:
- a circuit which precharges bit lines of a memory cell portion;
- and
- a circuit which precharges bit lines of a sense amplifier portion, wherein the bit lines of the memory cell portion and the bit lines of the sense amplifier portion are precharged independently of each other at different timings.
Dependencies are inferred from the claim text.