Code generation device, semiconductor device, and receiver device

A semiconductor device containing a code generation device for generating a predetermined code, comprising:

• a binary-data generation circuit which generates every (m+1)th binary data item of successive binary numbers from 0 to n, where m≧1 and n≧2;
• a binary-data derivation circuit which derives m+1 binary data items indicating m+1 binary numbers from a binary number indicated by each of said binary data items which are generated by the binary-data generation circuit, where the m+1 binary numbers include the binary number indicated by said each of said binary data items;
• a first processing circuit which performs a predetermined common operation on identical portions of the m+1 binary data items, where states of corresponding bits in the identical portions of the m+1 binary data items are identical;
• a second processing circuit which performs individually predetermined operations on non-identical portions of the m+1 binary data items, where states of corresponding bits in the non-identical portions of the m+1 binary data items are not identical;
• and
• a combining circuit which combines results of the operations by said first processing circuit and said second processing circuit.

A receiver device for generating a predetermined code, and demodulating a received signal by using the predetermined code, comprising:

• a binary-data generation circuit which generates every (m+1)th binary data item of successive binary numbers from 0 to n, where m≧1 and n≧2;
• a binary-data derivation circuit which derives m+1 binary data items indicating m+1 binary numbers from a binary number indicated by each of said binary data items which are generated by the binary-data generation circuit, where the m+1 binary numbers include the binary number indicated by said each of said binary data items;
• a first processing circuit which performs a predetermined common operation on identical portions of the m+1 binary data items, where states of corresponding bits in the identical portions of the m+1 binary data items are identical;
• a second processing circuit which performs individually predetermined operations on non-identical portions of the m+1 binary data items, where states of corresponding bits in the non-identical portions of the m+1 binary data items are not identical;
• and
• a combining circuit which combines results of the operations by said first processing circuit and said second processing circuit.