Method and circuitry for controlling clocks of embedded blocks during logic bist test mode

A method of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the method comprising:

• for each core,
• designating one of said at least one functional clock input as a core primary clock input and all other core functional clock inputs as secondary core clock inputs, said primary clock input being a clock input used to clock a core test controller;
• providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input;
• and
• for each secondary core functional clock input in said core:
• providing a core clock selection circuit for selecting one of a core functional clock signal output by said gating circuit and a core test clock signal and applying a selected signal to said each secondary core functional clock input;
• and
• for each functional clock input in said circuit, providing a second clock selection circuit for providing a corresponding core functional clock signal source, said second clock selection circuit being responsive to a mode signal for selecting between a functional clock signal source during normal operation of said circuit and a test clock signal source during testing of said circuit;
• and
• providing a test clock selection circuit associated with each secondary circuit clock input for selecting a clock signal derived from a circuit master clock input or from an associated circuit secondary clock input and providing a test clock signal output to a second clock selection circuit associated with the circuit secondary clock input.

A test clock distribution circuit for hierarchical integrated circuits having a plurality of embedded cores each having one or more functional clock inputs, comprising:

• each said core having:
• a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input;
• and
• a clock selection circuit for each secondary core functional clock input for selecting between a core functional clock signal output by said gating circuit and a core test clock signal.

An integrated circuit having embedded cores with each core having at least one core functional clock input, comprising:

• each said core having:
• a core primary clock input corresponding to the core functional clock input used to clock a core test controller, and secondary core functional clock inputs corresponding to all others of said at least one core functional clock inputs;
• a clock gating circuit for selectively disabling a core functional clock signal applied to said core primary clock input;
• a core clock selection circuit for each secondary core functional clock input in said core for selecting one of the core functional clock signal output by said gating circuit and a core test clock signal output by said test controller for a selected signal to said secondary core functional clock input;
• a second clock selection circuit for each functional clock input in said circuit for providing a core functional clock signal to corresponding core functional clock inputs, each said second clock selection circuit being responsive to a mode signal for selecting between a functional clock signal source during normal operation of said circuit and a test clock signal source during testing of said circuit;
• and
• a test clock selection circuit associated with each secondary circuit clock input for selecting a clock signal derived from a circuit master clock input or from an associated circuit secondary clock input and providing a test clock signal output to a second clock selection circuit associated the circuit secondary clock input.

A program product of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the program product comprising:

• a computer readable storage medium;
• means recorded on the medium for:
• for each core,
• providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input;
• and
• providing a core clock selection circuit for each secondary core functional clock input for selecting one of a core functional clock signal output by said gating circuit and a core test clock signal and applying a selected signal to said each secondary core functional clock input.

A program product of designing an integrated circuit for distributing test clock signals to embedded cores having at least one core functional clock input, the program product comprising:

• a computer readable storage medium;
• means recorded on the medium for:
• for each core,
• designating one of said at least one functional clock input as a core primary clock input and all other core functional clock inputs as secondary core clock inputs, said primary clock input being a clock input used to clock a core test controller;
• providing a clock gating circuit for selectively disabling a core functional clock signal applied to a core primary clock input;
• and
• for each secondary core functional clock input in said core:
• providing a core clock selection circuit for selecting one of a core functional clock signal output by said gating circuit and a core test clock signal and applying a selected signal to said each secondary core functional clock input;
• and
• for each functional clock input in said circuit, providing a second clock selection circuit for providing a corresponding core functional clock signal source, said second clock selection circuit being responsive to a mode signal for selecting between a functional clock signal source during normal operation of said circuit and a test clock signal source during testing of said circuit;
• and
• providing a test clock selection circuit associated with each secondary circuit clock input for selecting a clock signal derived from a circuit master clock input or from an associated circuit secondary clock input and providing a test clock signal output to a second clock selection circuit associated with the circuit secondary clock input.