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US 2003/0146776 A1Published application
Semiconductor device capable of maintaining output signal even if internal power supply potential is turned off
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYasunobu Nakase
Life of this patent
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Abstract
Even if a power supply potential VDD of a core section is set in an off state, a latch of a level conversion circuit holds a value corresponding to an output. It is, therefore, possible for a semiconductor device to hold an output state of an output node. Thereafter, an enable signal is deactivated, whereby the output node can be set in a high impedance state and a bus or the like can be released to the other device.
Claims17
A semiconductor device comprising:
- an internal circuit receiving a first power supply potential as an operating power supply potential, and outputting a first internal signal;
- and
- an interface circuit receiving, as the operating power supply potential, a second power supply potential capable of being maintained in an active state even if said first power supply potential is set in an inactive state, and driving an output node in accordance with said first internal signal, said interface circuit including
- a first level conversion circuit, said first level conversion circuit having
- a first holding circuit holding one of a first logical value and a second logical value complementary to said first logical value,
- a first write circuit writing one of said first and second logical values to said first holding circuit in accordance with said first internal signal, and
- a second write circuit writing said second logical value to said first holding circuit in accordance with an enable signal, and
- said interface circuit further including
- a driving section driving said output node if said first holding circuit holds said first logical value, and turning into a high impedance state with respect to said output node if said first holding circuit holds said second logical value.
6 more elements
A semiconductor device comprising:
- an internal circuit receiving a first power supply potential as an operating power supply potential, and outputting an internal signal, said internal circuit including
- a first pulse generation circuit activating said internal signal for a predetermined period in accordance with transition of a data signal;
- an interface circuit receiving, as the operating power supply potential, a second power supply potential capable of being maintained in an active state even if said first power supply potential is set in an inactive state, and driving an output node in accordance with said internal signal,
- said interface circuit includes
- a first level conversion circuit,
- said first level conversion circuit has
- a holding circuit holding one of a first logical value and a second logical value complementary to said first logical value, and
- a write circuit writing one of said first and second logical values to said holding circuit in accordance with said internal signal, and
- said interface circuit further includes
- a driving section driving said output node if said holding circuit holds said first logical value, and turning into a high impedance state with respect to said output node if said holding circuit holds said second logical value.
7 more elements
A semiconductor device comprising:
- a core section receiving, as operating power supply potentials, a first power supply potential and a second power supply potential, the second power supply potential capable of being maintained in an active state even if the first power supply potential is set in an inactive state, said core section including
- a first internal circuit receiving said first power supply potential as the operating power supply potential, and outputting an internal signal, and
- a second internal circuit operating in accordance with said internal signal, said second internal circuit having
- a level conversion circuit converting a logical amplitude of said internal signal, said level conversion circuit having
- a holding circuit holding one of a first logical value and a second logical value complementary to said first logical value, and
- a write circuit writing one of said first and second logical values to said holding circuit in accordance with said internal signal;
- and
- an interface circuit receiving a third power supply potential as the operating power supply potential, and mediating data communication between said core section and an outside of the semiconductor device.
5 more elements
A semiconductor device comprising:
- an internal circuit receiving a first power supply potential as an operating power supply potential, and outputting an internal signal;
- and
- an interface circuit receiving, as the operating power supply potential, a second power supply potential capable of being maintained in an active state even if said first power supply potential is set in an inactive state, and driving an output node in accordance with said internal signal, said interface circuit including
- a level conversion circuit converting level of said internal signal, said level conversion circuit including
- a level conversion section converting the level of a signal received at an input, and outputting the level-converted signal;
- and
- an input signal switching section applying said internal signal to the input of said level conversion section when a mode setting signal is active, feeding back an output of said level conversion section to the input of said level conversion section and separating said internal signal from the input of said level conversion section when the mode setting signal is inactive, and
- said interface circuit further includes
- a driving section driving said output node if the output of said level conversion circuit corresponds to a first logical value, and turning into a high impedance state with respect to said output node if the output of said level conversion circuit corresponds to a second logical value.
6 more elements
Dependencies are inferred from the claim text.