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US 2003/0146475 A1Published application
Pixel structure
AssigneeAu Optronics Corporation
InventorHan-Chung Lai
Life of this patent
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Abstract
A pixel structure comprising a thin film transistor, a pixel electrode, a scan line, a data line and an alignment mark. The alignment mark is formed beneath the data line. Misalignment is assessed through the degree of shifting between the alignment mark and the data line relative to each other. In addition, misalignment is also gauged through the degree of shifting between the alignment mark and the channel layer within the thin film transistor relative to each other.
Claims12
A pixel structure on a transparent substrate, comprising:
- a first conductive layer over the transparent substrate, wherein the first conductive layer includes a scan line, a gate electrode and an alignment mark and the gate electrode connects electrically with the scan line;
- a first dielectric layer over the transparent substrate and covering the first conductive layer;
- a channel layer over the first dielectric layer above the gate electrode;
- a second conductive layer over the first dielectric layer, wherein the second conductive layer includes a data line and a pair of source/drain terminals, the data line is above the alignment mark, and the gate electrode, the channel layer and the source/drain terminals together form a thin film transistor;
- a second dielectric layer over the first dielectric layer and covering the second conductive layer;
- and
- a pixel electrode over the second dielectric layer, wherein the pixel electrode and the data line are electrically connected to respective source/drain terminals.
4 more elements
A thin film transistor array, comprising:
- a first conductive layer over a transparent substrate, wherein the first conductive layer includes a plurality of scan lines, a plurality of gate electrodes and a plurality of alignment marks, and each gate electrode connects electrically with a corresponding scan line;
- a first dielectric layer over the transparent substrate and covering the first conductive layer;
- a plurality of channel layers over the first dielectric layer above the respective gate electrodes;
- a second conductive layer over the first dielectric layer, wherein the second conductive layer includes a plurality of data lines and a plurality of source/drain terminals with each data line formed over a corresponding alignment mark, and the gate electrodes, the channel layers and the source/drain terminals together form the thin film transistor array;
- a second dielectric layer over the second conductive layer;
- and
- a plurality of pixel electrodes over the second dielectric layer, wherein each set of pixel electrode and data line connects electrically with a pair of corresponding source/drain terminals.
4 more elements
Dependencies are inferred from the claim text.