Semiconductor memory cell and method of forming same
AssigneeHitachi, Ltd.
InventorsHideyuki Matsuoka, Kiyoo Itoh, Motoyasu Terao, Satoru Hanzawa, Takeshi Sakata
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Abstract
A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
Claims11
A semiconductor memory cell comprising:
- a plurality of word lines;
- a plurality of first and second wirings intersecting with at least one of said word lines by way of an insulating layer;
- and
- a plurality of memory cells formed at intersections of said word lines and said wirings, wherein
- said memory cell is composed of a vertical transistor with channel sections formed in the depth direction of said memory cell, and a material positioned above, containing at least tellurium.
A semiconductor memory cell comprising:
- a plurality of word lines;
- a plurality of wirings intersecting with said word lines by way of an insulating layer;
- and
- a plurality of memory cells formed at intersections of said word lines and said wirings, wherein
- said memory cell is composed of a vertical transistor with channel sections formed in the depth direction of said memory cell, and a material positioned above, containing at least tellurium.
A semiconductor memory cell comprising:
- a plurality of word lines;
- a plurality of first and second wirings intersecting with at least one of said word lines by way of an insulating layer;
- and
- a plurality of memory cells formed at intersections of said word lines and said wirings, wherein
- said memory cell is composed of a vertical transistor with channel sections formed in the depth direction of said memory cell, and a material positioned above with an electrically variable resistance.
A semiconductor memory cell comprising:
- a plurality of word lines;
- a plurality of wirings intersecting with said word lines by way of an insulating layer;
- and
- a plurality of memory cells formed at intersections of said word lines and said wirings, wherein
- said memory cell is composed of a vertical transistor with channel sections formed in the depth direction of said memory cell, and a material positioned above, with an electrically variable resistance.
Dependencies are inferred from the claim text.