Memory module with improved electrical properties
AssigneeInfineon Technologies AG
InventorsPeter Beer, Carsten Ohlhoff, Helmut Schneider
Life of this patent
Estimating the term…
Abstract
A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.
Claims10
A memory module, comprising:
- a substrate having an active region;
- a voltage generator outputting a reference potential;
- memory cells formed in said substrate and having capacitors and selection transistors, each of said capacitors having a first electrode and a second electrode being a counter electrode, said counter electrode being an electrically conductive region disposed in said substrate, said first electrode electrically conductively connected to a respective one of said selection transistors, said memory cells storing and outputting items of information and disposed in said active region of said substrate;
- dummy memory cells disposed adjoining said active region, said dummy memory cells not being used for storing the items of information, each of said dummy memory cells having a first dummy electrode and a second dummy electrode being a counter dummy electrode, said counter dummy electrode being an electrically conductive region disposed in said substrate, said counter dummy electrode being connectable to a voltage potential, said first dummy electrode electrically conductively connected to said voltage generator outputting the reference potential;
- bit lines connected to said selection transistors for accessing said memory cells;
- and
- word lines connected to and driving said selection transistors for reading out and/or writing in the items of information stored in said memory cells through said bit lines.
Dependencies are inferred from the claim text.