Capacitor for semiconductor integrated devices
AssigneeSTMicroelectronics S.r.I.
InventorsRaffaele Zambrano, Cesare Artoni
Life of this patent
Estimating the term…
Abstract
A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.
Claims46
A ferroelectric memory cell of a stacked type, comprising a MOS transistor formed in an active region of a substrate of semiconductor material and a ferroelectric capacitor formed on top of said active region, said MOS transistor having a conductive region, and said ferroelectric capacitor having a first electrode and a second electrode separated by a dielectric material region;
- said conductive region of said MOS transistor being connected to said first electrode of said ferroelectric capacitor through a contact region, characterized in that said ferroelectric capacitor has a non-planar structure.
A process for manufacturing a memory cell of a stacked type, comprising the steps of:
- forming a MOS transistor having a conductive region in an active region of a substrate of semiconductor material;
- forming, on top of said active region, a ferroelectric capacitor having a first and a second electrodes separated by a dielectric material region;
- and
- forming a contact region between said conductive region of said MOS transistor and said first electrode of said ferroelectric capacitor;
- characterized in that said ferroelectric capacitor has a non-planar structure.
A ferroelectric capacitor, comprising:
- a first electrode disposed on a surface and at least one side wall of a nonconductive pillar;
- a dielectric disposed on the first electrode adjacent to the surface and the at least one side wall;
- and
- a second electrode disposed on the dielectric adjacent to the surface and the at least one side wall.
A memory cell, comprising:
- a transistor;
- an insulator disposed on the transistor and including a first surface and including a projection having at least one side wall and having a second surface that is farther from the transistor than the first surface;
- and
- a ferroelectric capacitor disposed on the second surface and having a first electrode that is electrically coupled to the transistor.
A method for forming a ferroelectric capacitor, the method comprising:
- forming a first electrode on a surface and on at least one side wall of a pillar;
- forming a dielectric on the first electrode adjacent to the surface and to the at least one side wall;
- and
- forming a second electrode on the dielectric adjacent to the surface and to the at least one side wall.
Dependencies are inferred from the claim text.