Asynchronous crossbar with deterministic or arbitrated control
AssigneeFulcrum Microcystems Inc. A California Corporation
InventorsUri Cummings, Andrew Lines
Life of this patent
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Abstract
Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
Claims135
A crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information, each combination of an input channel and an output channel comprising one of a plurality of links, the crossbar comprising crossbar circuitry which is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information, wherein events on different links are uncorrelated.
A dispatcher which is operable to route an ordered stream of instructions received on a first number of input channels to designated ones of a second number of output channels according to instruction routing information, the dispatcher comprising dispatch circuitry which is operable to route the instructions to each output channel in a deterministic manner thereby preserving a partial ordering for each output channel defined in the ordered stream, wherein instructions on different output channels are uncorrelated.
An arbiter which is operable to route a plurality of instructions received on a first number of input channels to designated ones of a second number of output channels according to instruction routing information, the arbiter comprising arbitration circuitry which is operable to arbitrate between instructions received on different input channels and designating a same output channel, and prevent any of the different input channels from transmitting a subsequent instruction until arbitration between the different input channels is complete.
Dependencies are inferred from the claim text.