Semiconductor chip, chip stack package and manufacturing method

A chip stack package comprising:

• a circuit board having first contact pads and second contact pads;
• a lower semiconductor chip having an active surface, a back surface obverse to the active surface, a side surface between the active surface and the back surface, a plurality of bonding pads formed on the active surface, a plurality of bump pads formed on the back surface and corresponding to the bonding pad, and a plurality of connection lines formed on the back surface, each connection line being connected to the bump pad and extended to the side surface;
• at least one upper semiconductor chip having an active surface, a back surface obverse to the active surface, a side surface between the active surface and the back surface, a plurality of bonding pads formed on the active surface, a plurality of bump pads formed on the back surface and respectively corresponding to the bonding pads, and a plurality of connection lines formed on the back surface, each connection line being connected to the bump pad and extended to the side surface;
• a plurality of bumps electrically and physically connecting the bonding pads of the upper semiconductor chip to the bump pads of the lower semiconductor chip, and connecting the bonding pads of the lower semiconductor chip to the second contact pads of the circuit board;
• an interconnecting member applied to the side surfaces of both the lower semiconductor chip and the upper semiconductor chip, and connected to the first contact pads of the circuit board;
• and
• a plurality of outer terminals electrically connected to the circuit board.

A method of manufacturing a semiconductor chip, comprising:

• (a) providing a semiconductor wafer having a plurality of semiconductor chips and scribe lines, each semiconductor chip having bonding pads formed on an active surface, and each scribe line being formed between the adjacent semiconductor chips;
• (b) forming a plurality of grooves on a back surface obverse to the active surface;
• (c) forming a plurality of bump pads and connection lines by applying a conductive material in the grooves, each bump pad corresponding to each bonding pad, and each connection line being extended from the bump pad and exposed to the scribe line;
• and
• (d) separating the wafer along the scribe lines into the plurality of semiconductor chips.

A method of manufacturing a chip stack package, comprising:

• (a) providing a lower semiconductor chip and at least one upper semiconductor chip, each semiconductor chip having bonding pads formed on an active surface, bump pads formed on a back surface obverse to the active surface and respectively corresponding to the bonding pads, and connection lines formed on the back surface and respectively extended from the bump pads to a side surface between the active surface and the back surface;
• (b) providing a circuit board having first contact pads and second contact pads;
• (c) bonding, by using bumps, the bonding pads of the upper semiconductor chip to the bump pads of the lower semiconductor chip, and the bonding pads of the lower semiconductor chip to the second contact pads of the circuit board;
• (d) applying an interconnecting member to the side surfaces of both the lower semiconductor chip and the upper semiconductor chip such that the interconnecting member is electrically connected to the connection lines at the side surfaces and the first contact pads of the circuit board;
• and
• (e) forming outer terminals such that the outer terminals are electrically connected to the circuit board.