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US 2003/0145298 A1Published application
Integrated circuit analysis method and program product
AssigneeHewlett-Packard Development Company, L.P.
InventorsCharles Corey Pie, Gregory Louis Ranson
Life of this patent
Estimating the term…
Abstract
A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global transparency timing modeling.
Claims20
A method for making an integrated circuit model for an integrated circuit comprising the steps of:
- dividing the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks;
- and
- compressing each of said blocks by removing all of said latches from each of said blocks not required for modeling global transparency.
A method for making an integrated circuit timing model for modeling global transparency comprising the steps of:
- dividing the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block, each of said internal paths having a gate delay and a wire delay;
- summing said gate delays and said wire delays for each of said paths to determine a path delay for said each of said internal paths;
- removing latches from each of said blocks not required for modeling global transparency;
- and
- pruning said blocks by removing all incoming internal paths for each of said latches in each of said blocks except for said incoming path resulting in the largest path delay
2 more elements
A method for making an integrated circuit timing model comprising the steps of:
- dividing the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block, each of said internal paths having a gate delay, each of said internal paths having a wire delay, a plurality of said latches from each of said blocks having an on state defined between a latch start time and a latch end time, at least a first of said latches being connected to an incoming global path;
- compressing each of said blocks by calculating a representative path delay for each path using said gate delays and said wire delays;
- removing latches from each of said blocks not required for modeling global transparency by assigning a first latch arrival time for an incoming global signal for each of said blocks, determining a signal arrival time for said latches as said signal propagates through said each of said blocks, comparing said signal arrival time for respective of said latches with latch start times for said respective of said latches until a final latch is found having a latch start time later than said signal arrival time for said final latch, removing all latches in said each of said blocks downstream of said final latch except for latches connected to a global path;
- pruning said blocks by removing all incoming internal paths for each of said latches in each of said blocks except for said incoming path resulting in the largest path delay;
- identifying said latches in each of said blocks that are connected to more than one incoming global path;
- and
- creating a clone latch for each of said incoming global paths greater than one for each of said identified latches, moving one of said incoming global paths from each of said identified latches to one of said clone latches whereby each of said identified latches and each of said clone latches are connected to one incoming global path
4 more elements
A computer program product for modeling an integrated circuit comprising computer executable instructions stored in a computer readable medium that when executed cause a computer to:
- divide the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block;
- and
- compress each of said blocks by removing all of said latches not required for modeling global transparency.
A computer program product for modeling an integrated circuit comprising computer executable instructions stored on a computer readable medium that when executed cause a computer to:
- divide the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block, each of said paths having a gate delay equal to the sum of the delays for all gates along said path, each of said internal paths having a wire delay, at least a first of said latches being connected to an incoming global path;
- and
- compress each of said blocks by calculating a representative path delay for each path using said gate delays and said wire delays, remove latches for each of said blocks not required for modeling global transparency, and pruning said blocks by removing all incoming internal paths for each of said latches in each of said blocks except for said incoming path resulting in the largest path delay.
A computer program product for modeling an integrated circuit comprising computer executable instructions stored on a computer readable medium that when executed cause a computer to:
- divide the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks, each of said latches in each of said blocks having at least one internal path connected to others of said latches in said block, each of said paths having a gate delay equal to the sum of the delays for all gates along said path, each of said internal paths having a wire delay, at least a first of said latches being connected to an incoming global path;
- compress each of said blocks by calculating a representative path delay for each path using said gate delays and said wire delays, remove latches for each of said blocks not required for modeling global transparency, pruning said blocks by removing all incoming internal paths for each of said latches in each of said blocks except for said incoming path resulting in the largest path delay, identify said latches in each of said blocks that are connected to more than one incoming global path, create a clone latch for each of said incoming global paths greater than one for each of said identified latches, move one of said incoming global paths from each of said identified latches to one of said clone latches whereby each of said identified latches and each of said clone latches are connected to one incoming global path.
Dependencies are inferred from the claim text.