Critical path analysis
AssigneeSun Microsystems, Inc.
InventorAbhay Gupta
Life of this patent
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Abstract
Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.
Claims33
An apparatus for efficiently performing critical path analysis, the apparatus comprising:
- an input node coupled to a controlling input of a gate;
- an output node coupled to a non-controlling input of the gate;
- and
- a device coupled between the input and output nodes, the device having an I/O characteristic wherein:
- signals at both the input and output nodes rise and fall substantially simultaneously on a first edge;
- and
- on a remaining edge, a signal at the output node follows one of a rise and a fall of a signal at the input node after an output node delay,
- wherein the apparatus provides both rising and falling delays for the critical path analysis of the gate.
A method of efficiently performing critical path analysis, the method comprising:
- providing a device to assist in determining both rising and falling delays for the critical path analysis of a gate;
- coupling an input of the device to a controlling input of the gate;
- coupling an output of the device to a non-controlling input of the gate, the device having an I/O characteristic wherein:
- signals at both the input and output of the device rise and fall substantially simultaneously on a first edge;
- and
- on a remaining edge, a signal at the device output follows one of a rise and a fall of a signal at the device input after a output node delay;
- and
- determining the rising and falling delays for the critical path analysis of the gate utilizing the device.
A machine-readable medium that provides instructions which, when executed by a machine, cause the machine to perform operations comprising:
- providing a device to assist in determining both rising and falling delays for the critical path analysis of a gate;
- coupling an input of the device to a controlling input of the gate;
- and
- coupling an output of the device to a non-controlling input of the gate, the device having an I/O characteristic wherein:
- signals at both the input and output of the device rise and fall substantially simultaneously on a first edge;
- and
- on a remaining edge, a signal at the device output follows one of a rise and a fall of a signal at the device input after a output node delay.
An apparatus comprising:
- delay measurement means to provide both rising and falling delays for a critical path analysis of a gate;
- first coupling means to couple an input of the delay measurement means to a controlling input of the gate;
- second coupling means to couple an output of the delay measurement means to a non-controlling input of the gate;
- isolating means to logically isolate the delay measurement means output from the delay measurement means input;
- and
- determining means for determining the rising and falling delays for the critical path analysis of the gate.
Dependencies are inferred from the claim text.