System for controlling external models used for verification of system on a chip (SOC) interfaces
AssigneeInternational Business Machines Corporation
InventorsRobert J. Devins, Paul G. Ferro, Emory D. Keller, David W. Milton
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Abstract
A method and structure for a verification test bench system for testing an interface of a system-on-a-chip (SOC) that includes a verification interface model connected to the SOC interface and a test bench external bus interface unit (EBIU) connected to the verification interface model. The test bench EBIU is connected to a SOC EBIU within the SOC. The test bench EBIU and the SOC EBIU are mastered by the same processor in the SOC, such that the SOC interface and the verification interface model are programmed by the same test case running in the SOC.
Claims34
A verification test bench system for testing a system-on-a-chip (SOC) interface of an SOC, said verification test bench system comprising:
- a verification interface model connected to said SOC interface;
- and
- a test bench external bus interface unit (EBIU) connected to said verification interface model,
- wherein said test bench EBIU is connected to a SOC EBIU within said SOC.
A verification test bench system for testing a system-on-a-chip (SOC) interface of an SOC, said verification test bench system comprising:
- a verification interface model connected to said SOC interface;
- and
- a test bench external bus interface unit (EBIU) connected to said verification interface model,
- wherein said test bench EBIU is connected to a SOC EBIU within said SOC, and
- wherein said test bench EBIU and said SOC EBIU are mastered by the same processor in said SOC.
A verification test bench system for testing a system-on-a-chip (SOC) interface of an SOC, said verification test bench system comprising:
- a verification interface model connected to said SOC interface;
- and
- a test bench external bus interface unit (EBIU) connected to said verification interface model,
- wherein said test bench EBIU is connected to a SOC EBIU within said SOC, and
- wherein said test bench EBIU and said SOC EBIU are mastered by the same processor in said SOC, such that said SOC interface and said verification interface model are programmed by the same test case running in said SOC.
A method of testing a system-on-a-chip (SOC) interface of an SOC, said method comprising:
- connecting a verification interface model to said SOC interface;
- connecting a test bench external bus interface unit (EBIU) to said verification interface model;
- connecting said test bench EBIU to a SOC EBIU within said SOC;
- and
- comparing said SOC interface with said interface model.
A program storage device readable by machine tangibly embodying a program of instructions executable by the machine to perform a method for testing a system-on-a-chip (SOC) interface of an SOC, said method comprising:
- connecting a verification interface model to said SOC interface;
- connecting a test bench external bus interface unit (EBIU) to said verification interface model;
- connecting said test bench EBIU to a SOC EBIU within said SOC;
- and
- comparing said SOC interface with said interface model.
Dependencies are inferred from the claim text.