US 2003/0145287 A1 · Method and circuit arrangement for clock recovery

Abstract

Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Claims11

Dependent claims

A method for clock recovery from a transmitted data signal in synchronous digital systems, comprising the following steps:

producing at least four phase-shifted sample signals from a predetermined time signal,
selecting at least two of the sample signals as a function of the respective phase angle with respect to the data signal,
parallel time sampling the data signal with each selected sample signal, and
passing on one of the time-sampled data signals as a function of the respective phase separations between the data signal and the selected sample signals, to an output device.

1 more element

Dependencies are inferred from the claim text.

Method and circuit arrangement for clock recovery

Life of this patent

Method and circuit arrangement for clock recovery

Life of this patent

Abstract

Claims11