Test pattern generator and test pattern generation

A test pattern generator for testing a test circuit, comprising:

• a first read-only-memory unit, wherein the first read-only-memory unit holds test pattern data program codes and outputs test data signals;
• a second read-only-memory unit, wherein the second read-only-memory unit holds test pattern length codes and outputs test length signals;
• a counter electrically coupled to the first read-only-memory unit and the second read-only-memory unit, wherein the counter counts according to a test pattern cycle;
• a test circuit connector electrically coupled to the first read-only-memory unit and the second read-only-memory unit, wherein the test circuit connector outputs test result signals;
• a comparator, wherein the comparator holds a normal test result waveform, couples electrically with the test circuit, the first read-only-memory unit and the second read-only-memory unit and outputs an indicator signal;
• and
• a control device electrically coupled to the first read-only-memory unit, the second read-only-memory unit, the counter and the comparator, wherein the control device receives a control signal and outputs the indicator signal.

A test pattern generator for generating a test pattern to test a test circuit, comprising:

• a switching device for outputting a control signal;
• a field programmable gate array for receiving the control signal and test result signals and outputting test data signals, test length signals and an indicator signal;
• a test circuit connector for receiving the test data signals and the test length signals and outputting the test result signals;
• an output buffer for receiving the indicator signal and outputting an output signal;
• a display device for receiving the output signal;
• and
• an interface device electrically coupled with the switching device, the field programmable gate array, the test circuit connector, the output buffer and the display device.