Scanable R-S glitch latch for dynamic circuits
AssigneeSun Microsystems, Inc.
InventorJoseph R. Siegel
Life of this patent
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Abstract
A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.
Claims20
A dynamic sequential device comprising:
- a scan circuit that allows said dynamic sequential device to be scan controlled and observed.
A method of testing a dynamic sequential circuit capable of storing at least one bit, said method comprising the steps of:
- providing said dynamic sequential circuit with a scan circuit to control and determine a state of said dynamic sequential circuit;
- and
- controlling said scan circuit to determine said state of said dynamic sequential circuit using one or more clock signals and one or more control signals.
A method for in-circuit testing of a dynamic sequential device having a scannable test circuit, said method comprising the steps of:
- controlling said scannable test circuit to determine a state of said dynamic sequential device;
- and
- determining if said dynamic sequential device is able to operate as a dynamic sequential device based on said determined state of said dynamic sequential device.
A dynamic latch comprising:
- a test circuit adapted to allow in-circuit scan testing of said dynamic latch.
Dependencies are inferred from the claim text.