Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip floops
AssigneeSun Microsystems, Inc.
InventorsJoseph R. Siegel, David J. Greenhill, Ban-Pak Wong
Life of this patent
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Abstract
A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.
Claims39
A system for performance of scan control and observation on a circuit of said system, said system having a system clock that runs without interruption to synchronize said scan control and observation of said circuit with logical operation of said circuit, said system comprising:
- a clock control circuit synchronized by said system clock to control when said scan control and observation of said circuit occurs, wherein said system clock synchronizes one or more clock signals asserted by said clock control circuit, and
- a system controller to control operation of said scan control circuit, wherein said system controller provides said scan control circuit with a plurality of control signals for said performance of said scan control and observation of said circuit.
A method for performing scan testing of a logical circuit in an electronic system wherein said logical circuit includes a scan data path and a non-scan data path, said method comprising the steps of:
- providing said electronic system with a system clock that runs without interruption;
- halting data on said non-scan data path of said logical circuit, to allow scan data to propagate along said scan data path into said logical circuit;
- evaluating said scan data to determine an internal state of said logical circuit;
- outputting said evaluated scan data from said logical circuit over said scan data path for further evaluation by said electronic system;
- and
- allowing said data on said non-scan data path to propagate to allow said logical circuit to evaluate said non-scan data.
A method for scan control and observation of an integrated circuit having a scannable circuit, said method comprising the steps of:
- generating a system clock for said integrated circuit that runs continually during said scan control and observation of said electronic system;
- and
- controlling operation of said integrated circuit in synchronicity with said system clock to determine an internal state of said scannable circuit of said integrated circuit.
An integrated circuit comprising,
- a scannable logic element;
- a clock circuit coupled to a system clock that runs continuously to synchronize operation of said clock circuit;
- and
- a control circuit to control operation of said clock circuit, wherein said control circuit provides said clock circuit with control signals to control operation of said scannable logic element.
Dependencies are inferred from the claim text.