Variable self-time scheme for write recovery by low speed tester
AssigneeEtron Technology, Inc.
InventorsDer-Min Yuan, Bor-Doou Rong
Life of this patent
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Abstract
In accordance with the objectives of the invention a new method is provided for testing DRAM cells using a slow-speed tester. An adjustable self-time scheme is provided that is used for write-recovery during the testing of DRAM devices using a low-speed tester. CSL and WL pulses are self-time controlled and are in this manner used to emulate DRAM operation under different operational conditions. The adjustable self-time scheme of the invention can be used to screen write recovery (twr) depending on field requirements for the DRAM cell, a low-speed tester can be used for the screening.
Claims18
A method of performing high-speed memory testing using a low speed tester, comprising the steps of:
- forming a test circuit on a memory chip on a wafer, said test circuit performing a pulse-width generator function by modifying a sync pulse on the memory chip to produce a column select signal with controlled time-on period;
- forming a pulse turn-off generator on a memory chip of said wafer, said pulse turn-off generator modifying a write line signal with controlled turn-off delay;
- enabling said test circuit by connecting a clock signals and a sync signal from said tester to said test circuit;
- connecting a column select signal from said tester to said pulse turn-off generator of said test circuit of said memory chip, forming a column select signal with controlled time-on period;
- connecting a write line from said tester to said pulse turn-off generator on a memory chip, forming a modified write line signal with controlled turn-off delay;
- combining said column select signal with controlled time-on period with said modified write line signal with controlled turn-off delay, creating a write recovery period of the memory chip;
- and
- testing said memory chip to said write recovery period.
A test circuit for performing high-speed memory testing using a slow speed tester, comprising:
- forming a test circuit on a memory chip on a wafer, said test circuit performing a pulse-width generator function by modifying a sync pulse on the memory chip to produce a column select signal with controlled time-on period;
- forming a pulse turn-off generator on a memory chip of said wafer, said pulse turn-off generator modifying a write line signal with controlled turn-off delay;
- enabling said test circuit by connecting a clock signals and a sync signal from said tester to said test circuit;
- connecting a column select signal from said tester to said pulse turn-off generator of said test circuit of said memory chip, forming a column select signal with controlled time-on period;
- connecting a write line from said tester to said pulse turn-off generator on a memory chip, forming a modified write line signal with controlled turn-off delay;
- combining said column select signal with controlled time-on period with said modified write line signal with controlled turn-off delay, creating a write recovery period of the memory chip;
- and
- testing said memory chip to said write recovery period.
Dependencies are inferred from the claim text.