Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay
OwnerZhigang Hu, Stefanos Kaxiras +1inventors
InventorsZhigang Hu, Stefanos Kaxiras, Margaret Martonosi
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OwnerZhigang Hu, Stefanos Kaxiras +1inventors
InventorsZhigang Hu, Stefanos Kaxiras, Margaret Martonosi
Estimating the term…
An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.
A cache memory, comprising:
A method for reducing leakage power in a cache memory, said cache memory having a plurality of cache lines, said method comprising the steps of:
An integrated circuit, comprising:
Dependencies are inferred from the claim text.