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US 2003/0145239 A1Published application
Dynamically adjustable cache size based on application behavior to save power
OwnerWayne D. Kever, Eric S. Fetzerinventors
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OwnerWayne D. Kever, Eric S. Fetzerinventors
Estimating the term…
A circuit for reducing power in an on-chip cache memory on a microprocessor chip is implemented by dynamically controlling power applied to individual memory sections. Individual sections of memory are isolated from a fixed power supply by inserting one or more switches between GND and a negative connection of an individual memory section or by inserting one or more switches between VDD and a positive connection of an individual memory section. If a memory section is not accessed for a defined time, a PMU (Performance Monitor Unit) detects it and the power to that section is switched off, saving power. In addition, a software application may send information to the PMU to select the amount of cache memory needed for the particular software application.
1) A circuit for applying power to an on-chip cache memory array comprising:
8) A circuit for applying power to an on-chip cache memory array comprising:
15) A circuit for applying power to an on-chip cache memory array comprising:
22) A method for applying power to a on-chip cache memory array comprising:
29) A method for applying power to an on-chip cache memory array comprising:
36) A method for applying power to a cache memory array comprising:
Dependencies are inferred from the claim text.