Circuit and method for detecting multiple matches in a content addressable memory

Abstract

A priority encoder circuit for detecting multiple match in a CAM, the priority encoder comprising a plurality of inputs each for receiving a respective matchline signal, the inputs being arranged in a predetermined priority order and being enabled by a matchline signal being received thereon; a plurality of outputs corresponding to ones of said inputs; means for enabling one of the outputs corresponding to an enabled input, that is of the highest priority; and a circuit for logically combining a sufficient number of the inputs and outputs of the PE in order to determine whether more than one respective matchline signals has been received, the determination is based on an observation that for every match line input to the PE, there is a corresponding output from the PE and that the highest priority match should have the match line as well as its corresponding priority match output enabled and that if a match line output is enabled but its corresponding output is not, then there is another higher priority match line output; i.e. there must be multiple match line hits.

Dependencies are inferred from the claim text.