Mass storage device architecture and operation
AssigneeSaifun Semiconductor Ltd.
InventorsRan Dvir, Zeev Cohen, Eduardo Maayan
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AssigneeSaifun Semiconductor Ltd.
InventorsRan Dvir, Zeev Cohen, Eduardo Maayan
Estimating the term…
A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.
A mass storage device comprising:
The device according to claim 10, wherein said volatile data stored in the redundancy buffer is loaded from a non-volatile memory when the device is powered up.
A method for operation of a mass storage device, the method comprising:
Dependencies are inferred from the claim text.