Multiprocessor system having respective control programs of a plurality of processors stored contiguously in a memory
AssigneeDenso Corporation
InventorsShuji Agatsuma, Yoshinori Teshima, Kyoichi Suzuki
Life of this patent
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Abstract
A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a CPU identification register which stores an identification value for identifying the corresponding CPU. When a program which is specific to a CPU is to be executed by that CPU, the corresponding identification value is read out from the identification register of the CPU and is judged, and branching to the appropriate program is performed based on the judgement result.
Claims6
A multiprocessor system having a plurality of CPUs (central processing units), respective local buses connected to said CPUs, a memory having stored therein a plurality of control programs which are respectively executed by said CPUS, and a common bus which is connected to said memory and can be accessed via said local buses, said system comprising
- a plurality of data registers constituting identification registers, each connected only via a local bus to a corresponding one of said CPUs;
- wherein each of said identification registers has fixedly stored therein an identification value which is unique to said each register, and wherein each of said identification registers is adapted to respond to receiving a readout address which is supplied from the corresponding one of said CPUs by reading out and supplying to said corresponding CPU said stored identification value.
A multiprocessor system having n CPUs (central processing units), where n is a plural integer, respective local buses connected to said CPUs, a memory having stored therein a plurality of control programs which are respectively executed by said CPUs, and a common bus which is connected to said memory and can be accessed via said local buses, said system comprising
- (n−1) data registers constituting identification registers, each connected only via a local bus to a corresponding one of (n−1) of said CPUs, and
- data bus control circuit means, connected to a data bus of an n-th CPU which is a CPU other than said (n−1) CPUs having respective identification registers connected thereto,
- wherein each of said identification registers has fixedly stored therein an identification value which is unique to said each register, and wherein each of said identification registers is adapted to respond to receiving a readout address which is supplied from the corresponding one of said CPUs by reading out and supplying to said corresponding CPU said stored identification value, wherein said data bus control means is adapted to maintain a fixed bit pattern on said data bus during a condition in which memory access to said data bus of said n-th CPU is disenabled, and wherein said fixed bit pattern is different from respective bit patterns of said identification values of said (n−1) CPUs.
Dependencies are inferred from the claim text.