Reducing power in a snooping cache based multiprocessor environment

A method for reducing power in a snooping cache based environment comprising the steps of:

• receiving a request to access a memory address;
• determining a corresponding bit in a register associated with said requested memory address, wherein said register comprises a plurality of bits, wherein each bit in said register is associated with a segment of a system memory;
• and
• determining if said corresponding bit in said register associated with said requested memory address is set.

A system, comprising:

• a memory configured to store data;
• and
• a plurality of processing units coupled to said memory via a bus, wherein a processing unit comprises:
• a cache controller coupled to a cache memory associated with said processing unit, wherein said cache controller is configured to manage access to said cache memory, wherein said controller comprises is configured to snoop on said bus for a requested address issued from another processing unit of said system, wherein said cache controller is further configured to determine a corresponding bit in a register associated with said snooped requested address, wherein said cache controller is further configured to determine if said corresponding bit in said register associated with said snooped requested address is set, wherein if said corresponding bit in said register associated with said snooped requested address is not set, then a cache search of said cache memory is not performed.

A system, comprising:

• a memory configured to store data;
• a plurality of processing units coupled to said memory via a bus;
• and
• a bus interface unit coupling said plurality of processing units to said bus, wherein each of said plurality of processing units is configured to communicate to another processing unit via said bus interface unit, wherein a processing unit comprises:
• a processor;
• and
• a cache controller coupled to said processor and a cache memory associated with said processing unit, wherein said cache controller is configured to receive a request to access a memory address issued from said processor, wherein said cache controller is configured to determine a corresponding bit in a register associated with said requested memory address, wherein said cache controller is further configured to determine if said corresponding bit in said register associated with said requested memory address is set.

A system comprising:

• a memory configured to store data;
• and
• a plurality of processing units coupled to said memory via a bus, wherein a processing unit comprises:
• means for managing an access to a cache memory associated with said processing unit;
• means for snooping on said bus for a requested address issued from another processing unit of said system;
• means for determining a corresponding bit in a register associated with said snooped requested address;
• and
• means for determining if said corresponding bit in said register associated with said snooped requested address is set, wherein if said corresponding bit in said register associated with said snooped requested address is not set, then a cache search of said cache memory is not performed.

A system, comprising:

• a memory configured to store data;
• a plurality of processing units coupled to said memory via a bus;
• and
• a bus interface unit coupling said plurality of processing units to said bus, wherein each of said plurality of processing units is configured to communicate to another processing unit via said bus interface unit, wherein a processing unit comprises:
• a processor;
• means for receiving a request to access a memory address issued from said processor;
• means for determining a corresponding bit in a register associated with said requested memory address;
• and
• means for determining if said corresponding bit in said register associated with said requested memory address is set.