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US 2003/0145173 A1Published application
Context pipelines
AssigneeIntel Corporation
InventorsHugh M. Wilkinson III, Mark B. Rosenbluth, Matthew J. Adiletta, Debra Bernstein, Gilbert Wolrich
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Abstract
A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.
Claims25
A method comprises:
- assigning tasks for packet processing to a plurality of programming engines;
- establishing programming stages corresponding to the plurality of programming engines;
- and,
- establishing a plurality of pipelines between the programming stages.
1 more element
A processor comprising:
- a plurality of programming engines including:
- specific tasks for packet processing assigned to the plurality of programming engines;
- programming stages corresponding to the plurality of programming engines;
- a plurality of pipelines between the programming stages;
- and
- a plurality of contexts corresponding to the plurality of programming engines for the assigned tasks.
3 more elements
Dependencies are inferred from the claim text.