Simplified cache hierarchy by using multiple tags and entries into a large subdivided array
OwnerEric S. Fetzer, Eric DeLanoinventors
Life of this patent
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Abstract
A system and method for reducing the power and the size of a cache memory is implemented by creating a large cache which is subdivided into a smaller cache. One tag controls both the large cache and the smaller, subdivided cache. A second tag controls only the smaller cache. In addition to saving power and area, this system and method may be used to reduce the write-through and write-back effort, improve the latency and the coherency of a cache memory, and improve the ability of multiprocessor system to snoop cache memory.
Claims12
1) A cache memory system comprising:
- a first cache memory
- a second cache memory;
- a first tag electrically connected to said first cache memory;
- a second tag electrically connected to said first and said second cache memories;
- wherein said first cache memory is a subset of said second cache memory;
- wherein said first tag controls said first cache memory and said second tag controls said first and said second cache memories.
7) A method of reducing the physical size of a cache memory system comprising:
- fabricating a first tag and a second tag;
- fabricating a first cache memory;
- wherein a second cache memory is a subset of said first cache memory;
- wherein said second tag controls said second memory and said first tag controls said first and said second cache memories.
8) A method of reducing power in a cache memory system comprising:
- fabricating a first tag and a second tag;
- fabricating a first cache memory;
- wherein a second cache memory is a subset of said first cache memory;
- wherein said second tag controls said second memory and said first tag controls said first and said second cache memories.
9) A method of reducing the latency in cache memory system comprising:
- fabricating a first tag and a second tag;
- fabricating a first cache memory;
- wherein a second cache memory is a subset of said first cache memory;
- wherein said second tag controls said second memory and said first tag controls said first and said second cache memories.
10) A method of improving a write-through time of a cache memory system comprising:
- fabricating a first tag and a second tag;
- fabricating a first cache memory;
- wherein a second cache memory is a subset of said first cache memory;
- wherein said second tag controls said second memory and said first tag controls said first and said second cache memories.
11) A method of improving coherency of a cache memory system comprising:
- fabricating a first tag and a second tag;
- fabricating a first cache memory;
- wherein a second cache memory is a subset of said first cache memory;
- wherein said second tag controls said second memory and said first tag controls said first and said second cache memories.
12) A method of improving a write-through time of a cache memory system comprising:
- fabricating a first tag and a second tag;
- fabricating a first cache memory;
- wherein a second cache memory is a subset of said first cache memory;
- wherein said second tag controls said second memory and said first tag controls said first and said second cache memories;
- wherein a flush is implemented by moving said second cache memory to a different location within said first cache memory.
Dependencies are inferred from the claim text.