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US 2003/0145161 A1Published application
Apparatus and method to track command signal occurrence for dram data transfer
AssigneeIntel Corporation
InventorsNarendra S. Khandekar, Michael W. Williams, Howard S. David
Life of this patent
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Abstract
A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable this data trigger scheme to work even in heavily loaded configurations where there is more timing skew.
Claims26
An apparatus comprising:
- a controller to couple to a data bus and to a plurality of devices to transfer data between the devices and the data bus in response to a command signal, said controller to generate a chip select signal to select a particular device from the plurality of devices to respond to the command signal;
- and
- a logic unit coupled to generate a command occurrence signal based on timing of chip select signals to identify when command signals occur, the command occurrence signal to be asserted prior to the chip select signals to allow a flag signal to complete a data transfer.
An apparatus comprising:
- a memory to couple to a data bus to transfer data between said memory and bus in response to a command signal received to initiate data transfer and a flag signal received to complete the data transfer, said memory to operate as one of a plurality of memories in which a chip select signal selects said memory from the plurality of memories and wherein a flag signal operating in timing order with a command occurrence signal, which is based on timing of chip select signals to the plurality of memories, indicates timing when the data transfer is to occur following the command occurrence signal, the command occurrence signal to be asserted prior to the chip select signals to allow the flag signal to complete the data transfer;
- and
- a timing unit coupled to receive the command occurrence signal, flag signal and the chip select signal, said timing unit to generate a trigger signal in response to the flag signal to execute the data transfer, if the command occurrence signal and the chip select signal indicate that said memory is selected for the data transfer.
A system comprising:
- a controller to generate a command signal to initiate a data transfer in response to the command signal, said controller to generate a chip select signal, a rank select signal and a flag signal associated with the command signal;
- a bus coupled to said controller;
- and
- a plurality of memories coupled to said bus to transfer data between said memories and bus in response to the command signal generated by said controller, one of said plurality of memories being selected by the chip select signal for the data transfer in which the flag signal times the execution of the data transfer and the rank select signal times the occurrence of the command signal, the rank select signal to be asserted prior to the chip select signal to allow the flag signal to complete the data transfer.
1 more element
A method comprising:
- issuing a command signal to perform a read or write operation;
- issuing a chip select signal to select a particular memory device from a plurality of devices to perform a data transfer for the read or write operation;
- issuing a command occurrence signal to identify when the command signal is generated, the command occurrence signal being generated prior to the chip select signal;
- generating a flag signal subsequently in response to the issuing of the command signal to complete the data transfer;
- and
- capturing occurrences of the command occurrence signal, chip select signal and the flag signal in a memory device and generating a trigger signal when command occurrence, chip select and flag signals present are captured for the memory device, the trigger signal to execute the data transfer to complete the read or write operation in the memory device.
3 more elements
Dependencies are inferred from the claim text.