Embedded DRAM system having wide data bandwidth and data transfer data protocol

Abstract

A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation. The data communication system further includes a central data path in data communication for transferring data with the plurality of data paths. The central data path includes at least one junction circuit in data communication for transferring data, wherein a respective junction circuit of the at least one junction circuit includes circuitry for providing data communication between the central data path and at least one data path of the plurality of data paths. Each junction circuit further includes circuitry for controlling resetting of the junction circuit after data is transferred from the junction circuit for preparation of a subsequent data transfer operation.

Dependencies are inferred from the claim text.