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US 2003/0145156 A1Published application
Apparatus and method to track flag transitions for DRAM data transfer
AssigneeIntel Corporation
InventorsNarendra S. Khandekar, Michael W. Williams, Howard S. David
Life of this patent
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Abstract
A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable the data trigger scheme to work in a more heavily loaded configuration where there is more timing skew.
Claims29
An apparatus comprising:
- a memory to couple to a data bus to transfer data between said memory and bus in response to a command signal received to initiate the data transfer and a flag signal received to complete the data transfer;
- and
- a timing unit coupled to receive the command signal, flag signal and a memory select signal, said timing unit to generate a trigger signal in response to the flag signal to execute the data transfer, if the command signal indicates a command to transfer data and the memory select signal indicates that said memory is selected for the data transfer.
An apparatus comprising:
- a memory to couple to a data bus to transfer data between said memory and bus in response to a command signal received to initiate the data transfer and a flag signal received to complete the data transfer, said memory to operate as one of a plurality of memories, wherein a flag signal operating in timing order with the command signal indicates timing when the data transfer is to occur following the command signal;
- and
- a timing unit coupled to receive the command signal, flag signal and a chip select signal, said timing unit to generate a trigger signal in response to the flag signal to execute the data transfer, if the command signal indicates the data transfer and the chip select signal indicates that said memory is selected for the data transfer.
A system comprising:
- a controller to generate a command signal to initiate data transfer and also to generate a flag signal to time completion of the data transfer;
- a memory coupled to said controller to receive the command signal and complete the data transfer in response to the flag signal;
- a bus coupled to said memory to transfer data between said memory and bus in response to the flag signal;
- said controller to generate the command signal during a first clock period, along with a corresponding chip select signal to activate said memory to perform the data transfer, and the flag signal following the data transfer command signal at a later clock period;
- and
- said memory including a timing unit coupled to receive the command signal, flag signal and a chip select signal, said timing unit to generate a trigger signal in response to the flag signal to execute the data transfer, if the command signal indicates the data transfer and the chip select signal indicates that said memory is selected for the data transfer.
3 more elements
A method comprising:
- issuing a command signal to perform a read or write operation;
- issuing a chip select signal to select a particular memory device to perform a data transfer for the read or write operation;
- generating a flag signal subsequently in response to the issuing of the command signal to completes the data transfer;
- and
- capturing occurrences of the command signal, chip select signal and the flag signal in a memory device and generating a trigger signal when command, chip select and flag signals present are captured for the memory device, the trigger signal to execute the data transfer to complete the read or write operation in the memory device.
2 more elements
Dependencies are inferred from the claim text.