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AssigneeAdvanced Technology Materials, Inc.
InventorsPhilip C. Barnett, David Sowards
Estimating the term…
A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.
A single chip embedded microcontroller comprising,
A single chip embedded microcontroller comprising,
The single chip embedded microcontroller of claim 14 where said high voltage generator operates such that said two or more different erase and write voltages cannot be applied simultaneously to both of said first and second non-volatile PROM arrays and can only be applied to either of said first and second non-volatile PROM arrays.
The single chip embedded microcontroller of claim 14 in which said first and second non-volatile erasable PROM arrays are FLASH arrays.
The single chip embedded microcontroller of claim 14 in which said first non-volatile erasable PROM array is an OTPROM.
The single chip embedded microcontroller of claim 14 in which said second non-volatile erasable PROM array is an EEPROM.
The single chip embedded microcontroller of claim 17 in which said OTPROM contains an operating system which controls said single chip embedded microcontroller and alternately provides said two or more different erase and write voltages to said first and second non-volatile erasable PROM arrays.
The single chip embedded microcontroller of claim 17 having a ROM containing a program to load said OTPROM with an operating system, said ROM communicating with said processor.
Dependencies are inferred from the claim text.