Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus

A shared bus system comprising:

• N bus devices capable of requesting access to a shared bus;
• M tristate line drivers, each of said M tristate line drivers having an input for receiving a logic bit from one of said N bus devices and an output for outputting said received logic bit to said shared bus, wherein said each tristate line driver outputs said received logic bit when a line driver enable signal associated with said each tristate line driver is enabled and an output of said each tristate line driver is put into a high-impedance state when said line driver enable signal is disabled;
• and
• a bus arbitrator operable to slowly activate and rapidly de-activate said M tristate line drivers, said bus arbitrator comprising:
• an input interface capable of receiving a first bus access request signal from a first of said N bus devices;
• a delay circuit capable of receiving said first bus access request signal from said input interface and generating therefrom a time-delayed first bus access request signal;
• and
• a comparator circuit capable of receiving said first bus access request signal from said input interface and said time-delayed first bus access request signal from said delay circuit and generating a line driver enable signal only if both of said first bus access request signal and said time-delayed first bus access request signal are enabled.

For use in a shared bus system comprising N bus devices capable of requesting access to a shared bus, a method for slowly activating and rapidly de-activating a plurality of tristate line drivers coupled between the shared bus and the N bus devices, the method comprising the steps of:

• receiving a first bus access request signal from a first of the plurality of bus devices;
• generating from the first bus access request signal a time-delayed first bus access request signal;
• and
• comparing in a comparator circuit the first bus access request signal and the time-delayed first bus access request signal and generating a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled.