Method and apparatus for implementing a relaxed ordering model in a computer system

A system in communicating relationship with an I/O device and a computer memory system, the I/O device configured to issue a stream of memory reference operations, including read and write operations, and to specify the application of relaxed or strict ordering to the memory reference operations, the memory system having an ordering point configured to return commit signals to the system in response to memory reference operations becoming committed, the system comprising:

• a relaxed ordering controller;
• an epoch identifier (ID) generator operatively coupled to the relaxed ordering engine and configured to produce epoch ID values;
• and
• one or more payload commit pending counters operatively coupled to the relaxed ordering engine, wherein,
• the relaxed ordering engine
• organizes the stream of memory reference operations from the I/O device into epochs, such that the receipt of a first relaxed order write operation in the stream constitutes the start of an epoch and the receipt of a first strict order operation in the stream constitutes the conclusion of the epoch,
• upon the start of each epoch, directs the epoch ID generator to produce an epoch ID value for the respective epoch, and assigns a selected payload commit pending counter to the epoch ID value,
• associates the respective epoch ID value with all relaxed order write operations issued during the epoch,
• increments the selected payload commit pending counter in response to each relaxed order write operation issued during the epoch,
• decrements the selected payload commit pending counter in response to receiving a commit signal corresponding to a relaxed order write operation associated with the respective epoch ID, and
• delays completion of the strict order operation constituting the conclusion of the epoch until the selected payload commit pending counter reaches zero, thereby confirming that all relaxed order write operations issued during the epoch have committed.

A method for imposing relaxed ordering on a stream of memory reference operations issued by an input/output (I/O) device, including read and write operations, the operations indicating whether relaxed or strict ordering is to be applied, a computer memory system having an ordering point issues commit signals in response to memory reference operations becoming committed, the method comprising the steps of:

• organizing the stream of memory reference operations into epochs, such that the receipt of a first relaxed order write operation in the stream constitutes the start of an epoch and the receipt of a first strict order operation in the stream constitutes the conclusion of the epoch;
• upon the start of each epoch, producing an epoch ID value for the respective epoch, and assigning a payload commit pending counter to the epoch ID value;
• associating the respective epoch ID value with all relaxed order write operations issued during the epoch;
• incrementing the payload commit pending counter in response to each relaxed order write operation issued during the epoch;
• decrementing the payload commit pending counter in response to receiving a commit signal corresponding to a relaxed order write operation associated with the respective epoch ID;
• and
• delaying completion of the strict order operation constituting the conclusion of the epoch until the selected payload commit pending counter reaches zero, thereby confirming that all relaxed order write operations issued during the epoch have committed.