Ultra-fast adder
AssigneeSun Microsystems, Inc.
InventorHonkai Tam
Life of this patent
Estimating the term…
Abstract
A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.
Claims28
A method of generating carry information during an arithmetic operation of a first input signal A and second input signal B, the method comprising:
- generating a plurality of carry-create signals in response to logical combinations of corresponding first groups of bit pairings of the first and second input signals;
- generating a plurality of carry-transmit signals in response to logical combinations of corresponding second groups of bit pairings of the first and second input signals, wherein the first groups of bit pairings are different from the second groups of bit pairing;
- and
- logically combining the carry-create and carry-transmit signals to create a number of accumulated carry-create signals that represent accumulated carry information at predetermined bit intervals.
An adder for generating carry information during an arithmetic operation of a first input signal A and second input signal B, comprising:
- means for generating a plurality of carry-create signals in response to corresponding first groups of bit pairings of the first and second input signals;
- means for generating a plurality of carry-transmit signals in response to corresponding second groups of bit pairings of the first and second input signals, wherein the first groups of bit pairings are different from the second groups of bit pairings;
- means for logically combining the carry-create and carry-transmit signals to create a number of accumulated carry-create signals that represent accumulated carry information at predetermined bit intervals.
An adder for generating carry information during an arithmetic operation of a first input signal A and second input signal B, comprising:
- a plurality of carry-create circuits, each for generating a carry-create signal J in response to corresponding bit pairings of the input signals according to the logical expression J[z→x]=(Az|Bz)+(Ay|By)+(Ax|Bx), where | is the logical AND operation, + is the logical OR operation, and x, y, and z represent consecutive bit positions of the input signals;
- a plurality of carry-transmit circuits, each for generating a carry-transmit signal T in response to corresponding bit pairings of the input signals according to the logical expression T[z→x]=(Az+Bz)|[(Ay+By)|(Ax+Bx)+(Ay|By)];
- and
- carry look-ahead logic for logically combining the carry-create signals and the carry-transmit signals to generate a number of accumulated carry-create signals that represent accumulated carry information at predetermined bit intervals.
Dependencies are inferred from the claim text.