4:2 Compressor circuit for use in an arithmetic unit

An arithmetic multiplier suitable for use in a data processing system and including a compressor circuit, the compressor circuit comprising:

• a first stage configured to receive a set of four input signals and further configured to generate a first intermediate signal indicative of the XNOR of a first pair of the input signals and to generate a second intermediate signal indicative of the XNOR of a second pair of the input signals;
• a second stage configured to receive at least a portion of the signals generated by the first stage and further configured to generate first and second control signals, the first control signal indicative of the XNOR of the four input signals and the second control signal representing the logical complement of the first control signal;
• a carry circuit configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal;
• and
• a sum circuit configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal;
• wherein at least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate.

A data processing system including processor, memory, and I/O means, the processor including an arithmetic unit including a compressor circuit suitable for use in an arithmetic unit of a microprocessor, the compressor comprising:

• a first stage configured to receive a set of four input signals and further configured to generate a first intermediate signal indicative of the XNOR of a first pair of the input signals and to generate a second intermediate signal indicative of the XNOR of a second pair of the input signals;
• a second stage configured to receive at least a portion of the signals generated by the first stage and further configured to generate first and second control signals, the first control signal indicative of the XNOR of the four input signals and the second control signal representing the logical complement of the first control signal;
• a carry circuit configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal;
• and
• a sum circuit configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal;
• wherein at least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate.