Hub array system and method
AssigneeAxis Systems, Inc.
InventorSharon Sheau-Pyng Lin
Life of this patent
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Abstract
A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.
Claims39
A multi-board interconnect system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:
- a local bus interconnect separated from the motherboard connector and coupled to the system bus;
- a first board directly coupled to the motherboard via the motherboard connector and the local bus interconnect, and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements and the first logic bus coupled to the local bus interconnect;
- a second board directly coupled to the first board via the local bus interconnect and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements and the second logic bus coupled to the local bus interconnect, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the local bus;
- and
- a hub coupling the plurality of first hardware elements and plurality of second hardware elements.
An interconnect layout system for connecting a plurality of boards to a motherboard and to each other, where the motherboard contains a motherboard connector, comprising:
- at least one board and each board is designated board n, where n is a positive integer from 1 to N, and N represents a maximum number of desired boards;
- at least one logic device and each logic device is designated logic device m(n), where m is a positive integer from 1 to M, and M represents a maximum number of desired logic devices in a column on the board n;
- at least one horizontal connection and each horizontal connection is designated horizontal connection j(n), where j is a positive integer from 1 to J, and J represents a maximum number of desired horizontal connections, and the horizontal connections couple the logic devices in board n;
- at least one vertical interconnect and each vertical interconnect is designated vertical interconnect k, where k is a positive integer from 1 to K, and K represents a maximum number of desired vertical interconnects on the board n, and the vertical interconnect k couples the logic devices in adjacent board n and board n+1 and is spacially separated from the motherboard connector;
- and
- a hub coupling the logic devices together.
A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:
- an inter-board connection separated from the motherboard connector;
- a first board directly coupled to the motherboard via the motherboard connector and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements;
- a second board directly coupled to the first board via the inter-board connection and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the inter-board connection;
- a third board directly coupled to the second board via the inter-board connection and directly coupled to the motherboard via the motherboard connector, and the third board including a plurality of third hardware elements, wherein at least one of the plurality of second hardware elements in the second board is coupled to at least one of the plurality of third hardware elements in the third board via the inter-board connection;
- and
- a hub coupling the plurality of first hardware elements, second hardware elements, and third hardware elements together so that any hardware element can communicate with any other hardware element in two hops.
A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:
- an interboard connection separated from the motherboard connector;
- a first board directly coupled to the motherboard via the motherboard connector and including at least one row of a plurality of first logic devices and a first logic bus coupling the plurality of first logic devices;
- a second board directly coupled to the first board via the inter-board connection and including at least one row of a plurality of second logic devices and a second logic bus coupling the plurality of second logic devices, wherein the first board and second board collectively form an array of a plurality of rows and columns of logic devices;
- a hub provided for each column coupling the logic devices in that column, where each of the hubs in each column is coupled together.
37 A debug system for testing a user design, comprising:
- a plurality of logic devices for mapping and configuring a portion of the user design in hardware, wherein the plurality of logic devices are arranged in an array of rows and columns;
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- a plurality of hubs coupled together, wherein a hub is provided on each column coupling the plurality of logic devices in that column together.
The debug system of claim 37, wherein the plurality of logic devices can communicate with each other via the hubs in 2 hops.
The debug system of claim 37, wherein the hub contains logic and a portion of the user design.
Dependencies are inferred from the claim text.