Register repositioning method for functional verification systems
OwnerMichael I. Mandell, Timothy Koehler +1inventors
InventorsMichael I. Mandell, Timothy Koehler, Arnold L. Berman
Life of this patent
Estimating the term…
Abstract
A method and computer system formally verifies a synthesis of integrated circuit designs that include pipeline registers. A hardware description language (HDL) representation of an integrated circuit is parsed. Components and connections of the HDL representation are identified. Pipeline register components of the HDL representation are removed. The removed pipeline register components are replaced with a conductor. Pipeline register components are added between output logic gates and output registers of the HDL representation to create a new HDL representation. Formal verification of the new HDL representation is performed using a verification tool.
Claims16
A method for formally verifying a synthesis of an integrated circuit design that includes at least one pipeline register, comprising:
- parsing a hardware description language (HDL) representation of a said integrated circuit design;
- identifying components of said HDL representation;
- identifying connections between said components of said HDL representation;
- and
- removing at least one pipeline register component of said HDL representation.
A computer system that formally verifies a synthesis of an integrated circuit design that includes at least one pipeline register, comprising:
- a computer including a processor and memory;
- and
- a pipeline register repositioning module that is executed by said computer and that parses a hardware description language (HDL) representation of an integrated circuit, identifies components of said HDL representation and connections between said components of said HDL representation, and removes at least one pipeline register component of said HDL representation.
A method for formally verifying a synthesis of an integrated circuit design that includes at least one pipeline register, comprising:
- removing said at least one pipeline register component of a hardware description language (HDL) representation of said integrated circuit;
- and
- replacing said removed pipeline register component with a conductor;
- adding at least one pipeline register component between output logic gates and output registers of said HDL representation to create a new HDL representation.
A computer system that formally verifies a synthesis of an integrated circuit design that includes pipeline registers, comprising:
- a computer including a processor and memory;
- a verification module that is executed by said computer and that performs formal verification;
- a pipeline register repositioning module removes at least one pipeline register component of a hardware description level (HDL) representation, replaces said removed pipeline register component with a conductor, and adds at least one pipeline register component between output logic gates and output registers of said HDL representation to create a new HDL representation,
- wherein said verification module formally verifies said new HDL representation.
Dependencies are inferred from the claim text.