US 2003/0143854 A1 · Method of forming a shallow trench isolation in a semiconductor substrate

Abstract

A method of forming a shallow trench isolation in a semiconductor substrate. First, a hard mask consisting of a pad nitride and a pad oxide is formed on the semiconductor substrate. The semiconductor substrate is anisotrpically etched to form a trench while the hard mask is used as the etching mask. A thermal oxide film is grown on the trench. Then, a nitride liner is formed on the thermal oxide film. Next, a silicon rich oxide layer is conformally deposited on the nitride liner by high density plasma chemical vapor deposition without a bias voltage applied to the semiconductor substrate. Then, a silicon oxide is deposited to fill the trench by high density plasma chemical vapor deposition while a bias voltage is applied to the semiconductor substrate.

Claims7

Dependent claims

A method of forming a shallow trench isolation in a semiconductor substrate, comprising the steps of:

(a) forming a hard mask consisting of a pad nitride and a pad oxide on the semiconductor substrate;
(b) etching the semiconductor substrate to form a trench while the hard mask is used as the etching mask;
(c) forming a thermal oxide film on the trench;
(d) forming a nitride liner on the thermal oxide film;
(e) conformally depositing a silicon rich oxide layer on the nitride liner by high density plasma chemical vapor deposition without a bias voltage applied to the semiconductor substrate;
and
(f) forming a silicon oxide to fill the trench by high density plasma chemical vapor deposition while a bias voltage is applied to the semiconductor substrate.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/163,239Filed 4 Jun 2002

Priority

TW 9110134828 Jan 2002

Published

31 Jul 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10P 14/6336
Using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition: in the presence of a plasma [PECVD]
H10P 14/6506
Of treatments performed before formation of the materials: formation of intermediate materials
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Method of forming a shallow trench isolation in a semiconductor substrate

Life of this patent

Method of forming a shallow trench isolation in a semiconductor substrate

Life of this patent

Abstract

Claims7