FeRAM capacitor stack etch
OwnerFrancis G. Celii, Scott R. Summerfelt +1inventors
InventorsFrancis G. Celii, Scott R. Summerfelt, Mahesh Thakre
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Abstract
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
Claims22
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer using a BCl3 etch at a substantially high temperature in accordance with the patterned hard mask;
- and
- patterning the bottom electrode layer in accordance with the patterned hard mask.
A method of forming a capacitor stack in a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer using a Cl2+O2 or a Cl2+CO etch in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer using a BCl3+Ar etch at a temperature of about 150° C. or more in accordance with the patterned hard mask;
- and
- patterning the bottom electrode layer using a Cl2+O2 or a Cl2+CO etch in accordance with the patterned hard mask.
A method of forming a capacitor stack in a ferroelectric memory cell, comprising:
- forming an iridium bottom electrode layer, a PZT ferroelectric layer, an iridium top electrode layer, and a TiAlN hard mask layer over a substrate;
- patterning the TiAlN hard mask layer using a BCl3 etch;
- patterning the iridium top electrode layer using a Cl2+O2 or a Cl2+CO etch in accordance with the patterned hard mask, wherein an oxygen content in the iridium top electrode layer etch is at least about 5%, thereby providing a substantial etch selectivity with respect to the TiAlN hard mask;
- patterning the PZT ferroelectric layer using a BCl3+Ar etch at a temperature of about 150° C. or more in accordance with the patterned hard mask, wherein the temperature of about 150° C. or more provides for an etch of the PZT ferroelectric dielectric layer that is substantially selective with respect to the TiAlN hard mask;
- and
- patterning the bottom electrode layer using a Cl2+O2 or a Cl2+CO etch in accordance with the patterned hard mask, wherein an oxygen content in the iridium bottom electrode layer etch is at least about 5%, thereby providing a substantial etch selectivity with respect to the TiAlN hard mask.
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees;
- and
- patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 degrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch.
Dependencies are inferred from the claim text.