Twin MONOS cell fabrication method and array organization

A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising:

• providing a substrate having a memory area and a logic area;
• simultaneously defining a logic gate in said logic area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer;
• forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure;
• conformally depositing a polysilicon layer overlying said ONO layer;
• etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure;
• forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask;
• thereafter removing said polysilicon spacers in said logic area;
• etching back said polysilicon spacers in said memory area until a top surface of said polysilicon spacers is below a top surface of said first conducting layer of said memory gate and said logic memory boundary structure whereby said polysilicon spacers form control gates in said memory area;
• forming source/drain regions in said memory area using said control gates as an implantation mask;
• saliciding said control gates, said logic gates, and said source/drain regions;
• depositing an oxide layer overlying said salicided gates and source/drain regions and planarizing said oxide layer to a top surface of said cap nitride layer;
• removing exposed said cap nitride layer in said memory area to expose said first conducting layer;
• depositing a second conducting layer overlying said oxide layer and exposed said first conducting layer;
• and
• patterning said second conducting layer to form a word gate in said memory area to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.

A method of integrating the fabrication of a twin MONOS memory cell array and a CMOS logic device circuit comprising:

• providing a substrate having a memory area and a logic area;
• forming STI for memory cell isolation and logic active area isolation
• simultaneously defining a logic gate in said logic area and a memory gate in said memory area wherein a logic memory boundary structure is also formed wherein said logic gate comprises a gate oxide layer underlying a first conducting layer and wherein said memory gate and said logic memory boundary structure comprise a gate oxide layer underlying a first conducting layer underlying a cap nitride layer;
• forming an oxide-nitride-oxide (ONO) layer overlying said substrate, said logic gate, said memory gate, and said logic memory boundary structure;
• conformally depositing a polysilicon layer overlying said ONO layer;
• etching back said polysilicon layer to leave polysilicon spacers on sidewalls of said logic gate, said memory gate, and said logic memory boundary structure whereby said polysilicon spacers form control gates in said memory area;
• forming source/drain regions in said logic area using said logic gate and said polysilicon spacers as an implantation mask;
• thereafter removing said polysilicon spacers in said logic area;
• forming source/drain regions in said memory area using said control gates as an implantation mask;
• saliciding said control gates and said source/drain regions in said logic area;
• depositing an oxide layer overlying said salicided gates and source/drain regions;
• opening a contact hole through said oxide layer to a source/drain region in said memory area;
• and
• filling said contact hole with a tungsten layer to complete integration of said fabrication of said twin MONOS memory MONOS memory cell array and said CMOS logic device circuit.

A twin MONOS memory cell array and CMOS logic device circuit integrated circuit device comprising:

• a field implant memory cell isolation in a memory area;
• a salicided logic gate and an adjacent salicided source/drain region in a logic area;
• a memory gate and an adjacent salicided source/drain region in said memory area;
• control gates on sidewalls of said memory gate isolated from said memory gate by an oxide-nitride-oxide (ONO) layer;
• and
• a salicided word gate contacting said memory gate.

A twin MONOS memory cell array and CMOS logic device circuit integrated circuit device comprising:

• a shallow trench isolation for memory cell isolation and logic device isolation;
• a logic gate and an adjacent salicided source/drain region in a logic area;
• a memory gate and an adjacent source/drain region in a memory area;
• control gates on sidewalls of said memory gate isolated from said memory gate by all oxide-nitride-oxide (ONO) layer;
• and
• a local wiring through a dielectric level contacting said source/drain region in said memory area.

A twin MONOS memory cell array and CMOS logic device circuit integrated circuit device comprising:

• a shallow trench isolation for said memory device isolation along a direction of said bit line and a shallow trench isolation for said logic device isolation;
• logic gates and adjacent salicided source/drain regions in a logic area;
• dual metal bit lines to contact diffusions individually on each side of a memory gate in a memory area wherein said memory gate acts as a word line;
• control gates on sidewalls of said memory gate along said word line and adjacent source/drain diffusions wherein said control gates on sidewalls of said memory gate are isolated from said memory gate by a dielectric layer wherein a dielectric layer also underlies said control gates and wherein said word lines and said control gates are perpendicular to said bit lines;
• alternating extensions of said contact diffusions between said word lines along a bit line direction for bit contacts wherein said extensions of said contact diffusions on one side contact one of said dual metal bit lines and on the other side contact another of said dual metal bit lines;
• and
• a local wiring through a dielectric level contacting one of said source/drain regions in said memory area.

A twin MONOS memory cell array and CMOS logic device circuit integrated circuit device comprising:

• logic gates and adjacent salicided source/drain regions in a logic area;
• memory gates and adjacent source/drain regions in a memory area;
• control gates on sidewalls of said memory gates isolated from said memory gates by an oxide-nitride-oxide (ONO) layer
• word lines parallel to said control gates;
• a first diffusion area on one side of said word lines wherein said first diffusion area is divided into bits by shallow trench isolation regions;
• a second diffusion area on another side of said word lines wherein said second diffusion area forms a continuous diffusion line;
• and
• a metal line overlying said word lines and perpendicular to said word lines wherein said metal line contacts each of said bits of said first diffusion area and wherein said metal line acts as a bit line and wherein said metal line does not contact said continuous diffusion line and wherein said continuous diffusion line acts as a source line;