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US 2003/0143791 A1Published application
Methods for fabricating MOS transistors with notched gate electrodes
AssigneeSamsung Electronics Co., Ltd.
InventorsKong-Soo Cheong, Hee-Sung Kang
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Abstract
In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.
Claims26
A method for fabricating a MOS transistor, comprising:
- forming a multi-layered insulation layer, including at least two insulation layers, on a substrate;
- patterning the multi-layered insulation layer to form an opening exposing a predetermined region of the substrate, wherein the opening has a stair-shaped sidewall such that an upper portion of the opening is wider than a lower portion of the opening;
- forming a gate insulation layer on the exposed substrate;
- forming a gate electrode filling the opening on the gate insulation layer;
- and
- removing the multi-layered insulation layer to form a gate electrode having a notch region under an edge portion thereof.
3 more elements
Dependencies are inferred from the claim text.