Encapsulated integrated circuit package and method of manufacturing an integrated circuit package

A method of manufacturing an integrated circuit package, comprising:

• providing a substrate comprising:
• a first surface,
• a second surface opposite said first surface,
• a plurality of cavities, each said cavity through said substrate between said first and second surfaces, and
• a plurality of conductive vias, each said via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;
• applying a strip to said second surface of said substrate;
• mounting a plurality of semiconductor dies on said strip, at least a portion of each said semiconductor die being disposed inside each said cavity;
• encapsulating in a molding material at least a portion of said first surface of said substrate;
• and
• removing said strip from said substrate to expose a surface of each said semiconductor die.

An integrated circuit package comprising:

• a substrate comprising:
• a first surface,
• a second surface opposite said first surface,
• a cavity through said substrate between said first and second surfaces, and
• a conductive via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;
• a semiconductor die electrically coupled with said conductive via, at least a portion of said semiconductor die being disposed inside said cavity of said substrate;
• an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed.