US 2003/0143777 A1Published application

Super thin/super thermal ball grid array package

AssigneeST Assembly Test Services Ltd.

InventorsRaymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow

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Abstract

A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil. After this the processing for two embodiments of the invention again commonly proceeds with providing a black ink topping, performing an ink and post mold cure, attaching solder balls to the substrate, providing laser markings on the black ink topping, singulation of the die, inspection and testing after which the devices are packed and shipped as completed devices.

Claims15

Dependent claims

An ultra-thin semiconductor package, comprising:

a semiconductor substrate, said substrate having a first and a second surface, points of electrical contact having been provided in the second and the first surface of said substrate, said substrate having been provided with a cut-out through said substrate of a size allowing insertion of a semiconductor die therein, said insertion leaving a measurable distance between sidewalls of said die and an internal perimeter of said cut-out through said substrate;
an interconnect substrate comprising copper traces, said interconnect substrate having a first and a second surface, said first surface of said interconnect substrate being in contact with the second surface of the substrate, points of electrical interconnect being provided in the first substrate of said interconnect substrate, said points of electrical interconnect provided on said first surface of said interconnect substrate being in electrical contact with copper traces provided in said interconnect substrate, copper traces of said interconnect substrate being connected with points of electrical contact in or on the second surface of said substrate;
a solder mask having been provided on the first surface of said substrate, said solder mask exposing points of electrical contact provided in the first surface of said substrate;
a semiconductor die being inserted in said opening provided in said substrate, said semiconductor die having a first and a second surface, said first surface been provided with points of electrical contact, said second surface of said die being in contact with said first surface of said interconnect substrate, said second surface of said semiconductor die being about in a plane of said second surface of said substrate;
wire bond connections having been provided between points of electrical contact provided in said first surface of said semiconductor die and said points of electrical contact provided in or on said first surface of said substrate;
contact balls attached to said contact points provided in said first surface of said substrate, said contact balls having been inserted through openings provided in said solder mask;
a copper foil attached to the second surface of said interconnect substrate;
and
said semiconductor die and said wire bond connections and said first surface of said solder mask partially and in the immediate surroundings of said opening created in said substrate being embedded in a mold cap, said mold cap further penetrating between sidewalls of said semiconductor die and surrounding sidewalls of said opening created in said substrate.

6 more elements

A method of creating ultra-thin semiconductor packages, comprising the steps of:

(a) providing a substrate, said substrate comprising:
(i) a multiplicity of individual substrates, each individual substrate forming a substrate of said ultra-thin semiconductor package;
each individual substrate having a first and a second surface, points of electrical contact having been provided in the second surface of each individual substrate;
(ii) said substrate having a first and a second surface
(iii) an interconnect substrate comprising copper traces having been provided for each individual substrate provided in said substrate, said interconnect substrate provided for each individual substrate having a first and a second surface, said first surface of said interconnect substrate being in contact with said second surface of the substrate for each individual substrate;
(iv) a solder mask having a first and a second surface having been provided for each individual substrate provided in said substrate, said second surface of said solder mask being in contact with said first surface of the substrate for each individual substrate
(v) points of electrical contact having been provided in the first and the second surface of said substrate for each individual substrate provided in said substrate
(vi) points of electrical interconnect having been provided in the first surface of said interconnect substrate;
(vii) said points of electrical interconnect provided in said first surface of said interconnect substrate being connected with said traces of the interconnect substrate;
(viii) said points of electrical interconnect provided in the first surface of said interconnect substrate further being electrically connected with points of electrical interconnect provided in the second surface of each individual substrate;
(ix) said solder mask exposing points of electrical contact provided in the first surface of said substrate for each individual substrate provided in said substrate
(x) each individual substrate provided in said substrate further having been provided with a cut-out through said substrate of a size allowing insertion of a semiconductor die therein, said insertion leaving a measurable distance between sidewalls of said die and an internal perimeter of said cut-out through said substrate;
(b) optically inspecting said substrate;
(c) mounting and cutting said wafer to a desired die size;
(d) pre-baking said substrate;
(e) attaching a copper foil to the second surface of said interconnect substrate for each individual substrate;
(f) inserting a semiconductor die in said opening provided in said substrate for each individual substrate, said semiconductor die having a first surface and a second surface, said first surface having been provided with points of electrical contact for each individual substrate, said second surface of said semiconductor die being in contact with said first surface of said interconnect substrate for each individual substrate;
(g) curing said substrate;
(h) plasma cleaning exposed surfaces of said substrate;
(i) providing wire bond connections between points of electrical contact provided in said first surface of said semiconductor die and said points of electrical contact in said first surface of said substrate for each individual substrate;
(j) optically inspecting said substrate for defects such as poor or missing connections and surface impurities
(k) plasma cleaning exposed surfaces of said substrate;
(l) providing a mold compound surrounding the semiconductor die and the bond wires for each individual substrate, said mold compound molding partially overlapping the first surface of the solder mask that has been provided on the first surface of the substrate;
(m) providing a black ink topping on the second surface of said copper foil for each individual substrate;
(n) curing said black ink topping and said mold compound for each individual substrate;
(o) attaching solder balls to said points of electrical contact provided in said first surface of said substrate for each individual substrate, using the solder mask as a guide in placing the solder balls with respect to the substrate;
(p) providing laser marking overlying the black ink topping for each individual substrate;
(q) dividing or singulating said substrate into individual substrates, each individual substrate comprising a semiconductor die;
(r) optically inspecting the singulated substrates for irregularities;
(s) electrically testing the individual substrate;
(t) packaging individual substrates that pass the electrical testing;
and
(u) shipping the individual packages that have been packaged.

30 more elements

A method of creating ultra-thin semiconductor packages, comprising the steps of:

(a) providing a substrate, said substrate comprising:
(i) a multiplicity of individual substrates, each individual substrate forming a substrate of said ultra-thin semiconductor package;
each individual substrate having a first and a second surface, points of electrical contact having been provided in the second surface of each individual substrate;
(ii) said substrate having a first and a second surface
(iii) an interconnect substrate comprising copper traces having been provided for each individual substrate provided in said substrate, said interconnect substrate provided for each individual substrate having a first and a second surface, said first surface of said interconnect substrate being in contact with said second surface of the substrate for each individual substrate;
(iv) a solder mask having a first and a second surface having been provided for each individual substrate provided in said substrate, said second surface of said solder mask being in contact with said first surface of the substrate for each individual substrate
(v) points of electrical contact having been provided in the first and the second surface of said substrate for each individual substrate provided in said substrate
(vi) points of electrical interconnect having been provided in the first surface of said interconnect substrate;
(vii) said points of electrical interconnect provided in said first surface of said interconnect substrate being connected with said traces of the interconnect substrate;
(viii) said points of electrical interconnect provided in the first surface of said interconnect substrate further being electrically connected with points of electrical interconnect provided in the second surface of each individual substrate;
(ix) said solder mask exposing points of electrical contact provided in the first surface of said substrate for each individual substrate provided in said substrate
(x) each individual substrate provided in said substrate further having been provided with a cut-out through said substrate of a size allowing insertion of a semiconductor die therein, said insertion leaving a measurable distance between sidewalls of said die and an internal perimeter of said cut-out through said substrate;
(b) attaching a copper foil to the second surface of said interconnect substrate for each individual substrate;
(c) inserting a semiconductor die in said opening provided in said substrate for each individual substrate, said semiconductor die having a first surface and a second surface, said first surface having been provided with points of electrical contact for each individual substrate, said second surface of said semiconductor die being in contact with said first surface of said interconnect substrate for each individual substrate;
(d) providing wire bond connections between points of electrical contact provided in said first surface of said semiconductor die and said points of electrical contact in said first surface of said substrate for each individual substrate;
(e) providing a mold compound surrounding the semiconductor die and the bond wires for each individual substrate, said mold compound molding partially overlapping the first surface of the solder mask that has been provided on the first surface of the substrate;
(f) attaching solder balls to said points of electrical contact provided in said first surface of said substrate for each individual substrate, using the solder mask as a guide in placing the solder balls with respect to the substrate;
and
(g) dividing said substrate into individual substrates, each individual substrate comprising a semiconductor die.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/339,158Filed 9 Jan 2003
Priority: 30 May 2001
Published: 31 Jul 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10W 70/688
Characterised by their insulating layers or insulating parts: flexible insulating substrates
H10W 40/10
Arrangements for thermal protection or thermal control: arrangements for heating
H10W 70/682
Shapes or dispositions thereof: comprising holes having chips therein
H10W 70/685
Shapes or dispositions thereof: comprising multiple insulating layers

Family

Application09/867,095Division · filed 30 May 2001
Application10/339,158Division · filed 9 Jan 2003
US 2002/0180040 A1Published application
US 6,537,848 B2Related patent
US 6,744,125 B2Related patent
US 2003/0143777 A1This patent

From the US filing history. Foreign family members aren’t listed.