Method of fabrication lCOS structure

A liquid crystal on silicon structure, said liquid crystal on silicon structure comprising:

• a semiconductor substrate having a first conductivity;
• a complementary metal oxide semiconductor transistor on said semiconductor substrate;
• a capacitor on said semiconductor substrate and electrically separated to said complementary metal oxide semiconductor transistor;
• an interconnect structure on said complementary metal oxide semiconductor transistor and said capacitor, such that said complementary metal oxide semiconductor transistor is electrically coupled said capacitor;
• and
• a mirror layer is a top metallization layer of said interconnect structure and electrically coupled said interconnect structure.

A mix mode liquid crystal on silicon structure, said mix mode liquid crystal on silicon structure comprising:

• a semiconductor substrate having a first conductivity;
• a complementary metal oxide semiconductor transistor having a gate on said semiconductor substrate, and a source region having a second conductivity and a drain region having said second conductivity in said semiconductor substrate, said second conductivity opposite to said first conductivity, wherein said source region and said drain region in concentration of two well regions having said second conductivity is less than said source region and said drain region;
• an isolation structure in said semiconductor substrate and adjacent to said complementary metal oxide semiconductor transistor;
• a capacitor on said isolation structure;
• an inter-layer dielectric layer over said complementary metal oxide semiconductor transistor and said capacitor;
• a plurality of contact in said inter-layer dielectric layer and electrically coupled said drain region and said source region of said complementary metal oxide semiconductor transistor, such that said source region electrically coupled said drain region
• an interconnect structure electrically coupled said complementary metal oxide semiconductor transistor and said capacitor respectively, and wherein said interconnect structure on said inter-layer dielectric layer.

A method for forming a mix mode liquid crystal on silicon back plane, said method comprising:

• providing a semiconductor substrate having a first conductivity;
• forming an isolation structure on and in said semiconductor substrate;
• forming a first electrode plate of a capacitor on said isolation structure;
• sequentially forming a first oxide layer on said first electrode plate, a nitride layer on said first oxide layer, and a second oxide layer on said nitride layer;
• forming a gate oxide layer on said semiconductor substrate except for said second oxide layer, said nitride layer, said first oxide layer, and said first electrode plate;
• depositing a polysilicon layer on said semiconductor substrate and said second oxide layer;
• etching said polysilicon layer to form a gate on said semiconductor substrate and a second electrode plate on said second oxide layer;
• forming two well region having a second conductivity in said semiconductor substrate, said two well regions located adjacent said gate, wherein said second conductivity opposite to said first conductivity;
• forming a source region having a second conductivity and a drain region having said second conductivity in said two well regions, such that said source region, said drain region, and said gate constructing a complementary metal oxide semiconductor transistor and having a an operating voltage, and said complementary metal oxide semiconductor transistor located adjacent said isolation structure, wherein the concentration of said source region and said drain region is higher than said two well regions;
• forming an inter-layer dielectric on said semiconductor substrate, said complementary metal oxide semiconductor transistor, said isolation structure, and said capacitor;
• forming a plurality of contact in said inter-layer dielectric layer, and electrically coupled said source region, said drain region, said gate, and said first electrode plate and said second electrode plate of said capacitor;
• and
• forming a conductivity layer on said inter-layer dielectric layer,

A method for fabricating a mix mode liquid crystal on silicon back plane, said method comprising:

• providing a semiconductor substrate having a first conductivity;
• forming an isolation structure in and on said semiconductor substrate;
• forming a first electrode plate of a capacitor in said isolation structure;
• sequentially forming a first oxide layer on said first electrode plate, a nitride layer on said first oxide layer, and a second oxide layer on said nitride layer;
• forming a gate oxide layer on said semiconductor substrate except for said second oxide layer, said nitride layer, said first oxide layer, and said first electrode plate;
• depositing a polysilicon layer on said semiconductor substrate and said second oxide layer;
• etching said polysilicon layer and portion of said second oxide layer, said nitride layer, and said first oxide layer to form a gate on said semiconductor substrate and a second electrode plate on said second oxide layer, and the width of said second electrode plate and said second oxide layer, said nitride layer, and said first oxide layer is small than said first electrode plate;
• performing an ion implantation process to form two well regions having a second conductivity in said semiconductor substrate, said two well regions located adjacent side of said gate oxide, wherein said second conductivity opposite to said first conductivity;
• ion implanting a source region having said second conductivity and a drain region having said second conductivity in said semiconductor substrate, such that said source region, said drain region, and said gate constructing a complementary metal oxide semiconductor transistor and having a an operating voltage, and said complementary metal oxide semiconductor transistor located adjacent said isolation structure, wherein the concentration of said source region and said drain region is higher than said two well regions;
• depositing an inter-layer dielectric layer on said semiconductor substrate, said complementary metal oxide semiconductor transistor, said isolation structure, and said capacitor;
• forming a plurality of contact in said inter-layer dielectric layer and electrically coupled said source region, said drain region, and said gate of said complementary metal oxide semiconductor transistor, said first electrode plate and said second electrode plate of said capacitor, wherein said plurality of contact at least on said first electrode plate;
• forming a conductivity layer on said inter-layer dielectric layer;
• and
• forming an interconnect structure on said conductivity layer.