Method of manufacturing a semiconductor device
AssigneeHitachi, Ltd.
InventorHiroshi Fukuda
Life of this patent
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Abstract
Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.
Claims10
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a first pattern having alignment marks on a semiconductor substrate;
- forming a resist film on the surface of the first pattern;
- and
- aligning a second pattern formed on a mask with each of the alignment marks and transferring the second pattern onto the resist film
- wherein upon execution of the alignment, a step for measuring asymmetry of each of the alignment marks and a step for executing the alignment based on the result of measurement are included.
A method of manufacturing a semiconductor device, comprising the steps of:
- in a processing equipment having a step for effecting coating/baking of a resist film onto a wafer having alignment marks, and a step for developing the wafer,
- measuring asymmetry of each of the alignment marks;
- and
- measuring critical dimensions of the resist pattern,
- wherein the asymmetry measurement and the critical dimension measurement are performed by the same measuring apparatus disposed in the processing equipment.
A method of manufacturing a semiconductor device, comprising a series of steps of:
- effecting coating/baking of a resist on each of wafers having alignment marks to form a resist film;
- and
- exposing and developing patterns placed on a mask onto the resist film,
- wherein a processing sequence for shifting a staring point of the series of steps one by one and advancing processing is provided for each wafer, and
- wherein after the resist coating/baking step, a step for measuring asymmetry of each of the alignment marks is provided and a step for measuring critical dimensions of the resist pattern after the exposure and development is provided.
A method of manufacturing a semiconductor device, comprising the steps of:
- a plural pattern forming step including a step for forming a gate electrode of a field effect transistor;
- and
- aligning a wafer having alignment marks with a mask upon the plural pattern forming step,
- wherein upon the alignment, a step for measuring asymmetry of each of the alignment marks is applied to at least the gate electrode forming step.
A method of manufacturing a semiconductor device, comprising the steps, upon alignment of a wafer having alignment marks with a mask:
- measuring asymmetry of each of the alignment marks;
- measuring pattern dimensions on the mask and dimensions of patterns on the mask, which have been transferred onto the wafer and deriving discrepancy from the result of measurement;
- and
- obtaining a correlation line from the result of measurement of the asymmetry and the discrepancy,
- wherein the amount of offset for the alignment is determined based on the correlation line and a position adjustment to the alignment is performed using the amount of offset.
Dependencies are inferred from the claim text.