Fast skew detector

A method for receiving communication signals from a transmitter transmitted over multiple parallel channels, including a first channel and at least one second channel, the signals on the first channel carrying a first sequence of first symbols, and the signals on the at least one second channel carrying at least one second sequence of second symbols, which are transmitted by the transmitter in a predetermined relation to the first symbols, comprising:

• processing the signals received on the multiple parallel channels so as to extract therefrom at least the first and second sequences of symbols;
• receiving and storing in a first-in-first-out (FIFO) memory at least one bit of each of the received symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval;
• determining for each of the received symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, based on the predetermined relation between the first and second symbols;
• and
• performing comparisons between the expected value and the at least one bit of each of the received second symbols in the FIFO memory, so as to determine a relative skew between the first and at least the second channel.

In a data receiver for receiving communication signals from a transmitter over multiple parallel channels, including a first channel and at least one second channel, the signals on the first channel carrying a first sequence of first symbols, and the signals on the at least one second channel carrying at least one second sequence of second symbols, which are transmitted by the transmitter in a predetermined relation to the first symbols, signal processing apparatus comprising:

• an input circuit, which is coupled to process the signals received on the multiple parallel channels so as to extract therefrom at least the first and second sequences of symbols;
• a first-in-first-out (FIFO) memory, which is coupled to the input circuit so as to receive and store at least one bit of each of the received symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval;
• a symbol predictor, which is adapted, based on the predetermined relation between the first and second symbols, to determine for each of the received symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval;
• and
• comparison logic, which is adapted to compare the expected value with the at least one bit of each of the received second symbols in the FIFO memory, so as to determine a communication mode between the transmitter and the data receiver.