Pipelining of multiplexer loops in a digital circuit

A digital logic circuit for determining an output value based on a plurality of inputs values, comprising:

• an n-level look-ahead network that converts the plurality of input values to a plurality of intermediate values;
• a plurality of multiplexers each having a first and a second input port, an output port, and a control port, the plurality of multiplexers arranged to form a pipelined multiplexer loop, the pipelined multiplexer loop being coupled to the n-level look-ahead network;
• a first communications link that couples the output port of a first multiplexer to the first input port of a second multiplexer;
• a second communications link that couples the output port of a third multiplexer to the second input port of the second multiplexer;
• a first feedback loop that couples the output port of the second multiplexer to the control port of the second multiplexer, the first feedback loop comprising a first delay device having a first delay time;
• and
• a second feedback loop that couples the output port of the second multiplexer to the control ports of the first and third multiplexers, the second feedback loop comprising the first delay device and a second delay device having a second delay time,
• wherein the first delay time is an integer multiple of the second delay time and is equal to (n+1) times a clock period of operation of the digital logic circuit.

A method for pipelining multiplexer loops that form part of an integrated circuit, the method comprising the steps of:

• (a) selecting a number of input values to be provided to a pipelined multiplexer loop during a clock period of operation of the integrated circuit;
• (b) selecting a number of look-ahead steps to be implemented as a part of the pipelined multiplexer loop;
• and
• (c) implementing the pipelined multiplexer loop using at least one digital logic circuit, comprising:
• an n-level look-ahead network that converts the number of input values selected in step (1) to a plurality of intermediate values, wherein n represents the number of look-ahead steps selected in step (2),
• a plurality of multiplexers each having a first and a second input port, an output port, and a control port, the plurality of multiplexers arranged to form the pipelined multiplexer loop, the pipelined multiplexer loop having at least a first and a second stage, the first stage consisting of a first multiplexer, and the second stage consisting of a second and a third multiplexer, the pipelined multiplexer loop being coupled to the n-level look-ahead network,
• a first communications link that couples the output port of the second multiplexer to the first input port of the first multiplexer,
• a second communications link that couples the output port of the third multiplexer to the second input port of the first multiplexer,
• a first feedback loop, having a first delay time, that couples the output port of the first multiplexer to the control port of the first multiplexer, and
• a second feedback loop, having a second delay time, that couples the output port of the first multiplexer to the control ports of the second and third multiplexers,
• wherein the first delay time is an integer multiple of the second delay time and is equal to (n+1) times a clock period of operation of the integrated circuit.