Electrically programmable resistance cross point memory structure
AssigneeSharp Laboratories of America, Inc.
InventorsSheng Teng Hsu, Wei-Wei Zhuang
Life of this patent
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Abstract
Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
Claims32
A memory structure comprising;
- a) a substrate;
- b) a plurality of bottom electrodes overlying the substrate;
- c) a plurality of top electrodes overlying the bottom electrodes;
- and
- d) a continuous active layer interposed between the plurality of top electrodes and the plurality of bottom electrodes.
A method of manufacturing a memory structure comprising the steps of:
- a) providing a semiconductor substrate;
- b) forming a plurality of bottom electrodes;
- c) depositing a layer of perovskite material overlying the bottom electrodes;
- d) removing the layer of perovskite material from regions outside a memory array area, whereby the layer of perovskite material remains within the memory array area;
- and
- e) forming a plurality of top electrodes overlying the layer of perovskite material.
A memory circuit for a resistive memory bit comprising:
- a) a bit line connected to the resistive memory bit;
- b) a bit pass transistor, having a gate, a first source/drain and a second source/drain, wherein the first source/drain is connected to the bit line;
- c) an inverter, having an input connected to the second source/drain;
- and
- d) a load transistor connected between the inverter and ground, wherein the load transistor has a load gate.
A method of changing resistivity of a bit within a memory array comprising the steps of:
- a) providing the bit formed at the cross point of a word, line and a bit line with a perovskite active layer interposed between the word line and the bit line, wherein the bit line is connected through a bit pass transistor having a bit pass gate, to a load transistor, having a load gate, connected to ground;
- b) applying a programming voltage to the word line;
- c) applying a first on voltage to the bit pass gate, whereby current is allowed to flow through the bit pass transistor;
- and
- d) applying a second on voltage to the load gate, whereby current is allowed to flow through the load transistor, such that current flows through the active layer to change the resistivity of the bit.
A method of reading a bit having multiple resistivity states within a memory array comprising the steps of:
- a) providing the bit formed at the cross point of a word line and a bit line with a perovskite active layer interposed between the word line and the bit line, wherein the bit line is connected through a bit pass transistor, having a bit pass gate, to an inverter, with a load transistor, having a load gate, connected between the inverter and ground;
- b) applying a readout voltage to the word line;
- c) applying an on voltage to the bit pass gate, whereby current is allowed to flow through the bit pass transistor;
- d) applying a load voltage to the load gate, whereby current above a saturation current of the load transistor is allowed to flow through the load transistor, and current below the saturation current will not flow through the load transistor;
- and
- e) reading an output voltage from the inverter.
Dependencies are inferred from the claim text.