Memory controller and serial memory
AssigneeDenso Corporation
InventorsAkimasa Niwa, Takayuki Aono, Takuya Harada
Life of this patent
Estimating the term…
Abstract
In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.
Claims7
A memory controller for controlling memories by utilizing serial data, comprising:
- interface means for inputting at least serial data including an instruction bit train with addition of a start bit at the beginning thereof, a clock signal synchronized with the serial data, a chip enable signal for designating a relevant apparatus and a reset signal for resetting the relevant apparatus;
- serial data storing means for storing the serial data depending on the clock signal during an active period in which the chip enable signal is inputted;
- access control means for executing a memory access depending on content of the instruction bit train stored in the serial data storing means;
- enabling signal generating means for generating an enabling signal to enable operation of the access control means based on the an timing of the active period;
- and
- inhibiting means for inhibiting generation of the enabling signal based on the active period end timing when the relevant apparatus is reset during the active period.
A memory controller for controlling memories by utilizing serial data, comprising:
- interface means for inputting at least serial data including an instruction bit train with addition of a start bit at the beginning thereof, a clock signal synchronized with the serial data, and a chip enable signal for designating a relevant apparatus;
- serial data storing means for storing the serial data depending on the clock signal during an active period in which the chip enable signal is inputted;
- access control means for executing memory access depending on content of the instruction bit train stored in the serial data storing means;
- enabling signal generating means for generating an enabling signal to enable operation of the access control means based on the end timing of the active period;
- and
- another inhibiting means for inhibiting generation of the enabling signal when the data stored in the serial data storing means during the active period does not reach a predetermined bit length.
Dependencies are inferred from the claim text.