Capacitive techniques to reduce noise in high speed interconnections
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
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AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Estimating the term…
Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. The method includes forming a first layer of insulating material on the first layer of the electrically conductive material. The first layer has a thickness of less than 1.0 micrometers (μm). A transmission line is formed on the first layer of insulating material. The transmission line has a thickness and a width of approximately 1.0 micrometers. A second layer of insulating material is formed on the transmission line. And, a second layer of electrically conductive material is formed on the second layer of insulating material.
A method for forming transmission lines in an integrated circuit, comprising:
A method for forming integrated circuit lines, comprising:
A method for forming transmission lines in a memory device, comprising:
The method of claim 16, wherein forming the first pair of electrically conductive lines includes forming the electrically conductive lines to have a thickness and a width of approximately 1.0 μm.
A method of forming a memory device, the method comprising:
A transmission line circuit, comprising:
A differential line circuit in a Dynamic Random Access Memory (DRAM), comprising:
An electronic system comprising:
Dependencies are inferred from the claim text.